ep3c120f780c8nes Altera Corporation, ep3c120f780c8nes Datasheet - Page 300

• Manufacturer Part Number: ep3c120f780c8nes
• Description: Cyclone Iii Device Family
• Manufacturer: Altera Corporation

Configuring Cyclone III Devices
10–64
Cyclone III Device Handbook, Volume 1
In Cyclone III devices, the initialization clock source is either the internal
oscillator (typically 10MHz) or the optional CLKUSR pin. By default, the
internal oscillator is the clock source for initialization. If the internal
oscillator is used, the Cyclone III device provides itself with enough clock
cycles for proper initialization. Therefore, if the internal oscillator is the
initialization clock source, sending the entire configuration file to the
device is sufficient to configure and initialize the device. Driving DCLK to
the device after configuration is complete does not affect device
operation. Additionally, if you use the internal oscillator as the clock
source, you can use the CLKUSR pin as a user I/O pin.
You can also synchronize initialization of multiple devices or to delay
initialization with the CLKUSR option. The Enable user-supplied start-
up clock (CLKUSR) option can be turned on in the Quartus II software
from the General tab of the Device & Pin Options dialog box. Supplying
a clock on CLKUSR does not affect the configuration process. The
CONF_DONE pin goes high one byte early in FPP configuration mode.
The last byte is required for serial configuration (AS and PS) modes. After
the CONF_DONE pin transitions high, CLKUSR is enabled after the time
specified as t
require 3,180 clock cycles to initialize properly and enter user mode.
Cyclone III devices support a CLKUSR f
An optional INIT_DONE pin is available, which signals the end of
initialization and the start of user-mode with a low-to-high transition.
This Enable INIT_DONE Output option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If the INIT_DONE pin is used, it is high because of an external 10 KΩ
pull-up resistor when nCONFIG is low and during the beginning of
configuration. Once the option bit to enable INIT_DONE is programmed
into the device (during the first frame of configuration data), the
INIT_DONE pin goes low. When initialization is complete, the
INIT_DONE pin is released and pulled high. The MAX II device must be
able to detect this low-to-high transition, which signals the device has
entered user mode. When initialization is complete, the device enters user
mode. In user-mode, the user I/O pins no longer have weak pull-up
resistors and function as assigned in your design.
To ensure DCLK and DATA[7..0] are not left floating at the end of
configuration, the MAX II device must drive them either high or low,
whichever is convenient on your board. The DATA[7..0] pins are
available as user I/O pins after configuration. When you select the FPP
scheme in the Quartus II software, these I/O pins are tri-stated in user
mode by default. To change this default option in the Quartus II software,
select the Dual-Purpose Pins tab of the Device & Pin Options dialog box.
CD2CU
. After this time period elapses, Cyclone III devices
MAX
Altera Corporation-Preliminary
of 133 MHz.
March 2007