ep3c120f780c8nes Altera Corporation, ep3c120f780c8nes Datasheet - Page 174

• Manufacturer Part Number: ep3c120f780c8nes
• Description: Cyclone Iii Device Family
• Manufacturer: Altera Corporation

Cyclone III Device I/O Features
Termination
Scheme for
I/O Standards
7–22
Cyclone III Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
(4)
LVPECL
Table 7–5. Cyclone III Supported I/O Standards and Constraints (Part 3 of 3)
I/O Standard
The PCI-clamp diode needs to be enabled for 3.3-V/3.0-V LVTTL/LVCMOS.
Differential HSTL and SSTL outputs use two single-ended outputs with the second output programmed as
inverted. Differential HSTL and SSTL inputs treat differential inputs as two single-ended HSTL and SSTL inputs
and only decode one of them. Differential HSTL and SSTL only supported on CLK pins.
PPDS, mini-LVDS, and RSDS are only supported on output pins.
LVPECL is only supported on clock inputs.
Table
(4)
7–5:
Differential
Type
This section describes the recommended termination schemes for
voltage-referenced and differential I/O standards.
The following I/O standards do not specify a recommended termination
scheme per the JEDEC standard:
■
■
■
■
■
■
■
Voltage-Referenced I/O Standard Termination
Voltage-referenced I/O standards require both an input reference voltage
(V
receiving device tracks the termination voltage of the transmitting device,
as shown in
REF
3.3-V LVTTL
3.0-V LVTTL and LVCMOS
2.5-V LVTTL and LVCMOS
1.8-V LVTTL and LVCMOS
1.5-V LVCMOS
1.2-V LVCMOS
3.0-V PCI and PCI-X
Standard
Support
) and a termination voltage (V
—
Figures 7–10
2.5 V
Input
V
CCIO
Level
and 7–11.
Output
—
CLK,
DQS
TT
v
Top and Bottom I/O
). The reference voltage of the
PLL_
OUT
Pins
Altera Corporation-Preliminary
User I/O
Pins
CLK,
DQS
Side I/O Pins
v
March 2007
User I/O
Pins