ep3c120f780c8nes Altera Corporation, ep3c120f780c8nes Datasheet - Page 132

• Manufacturer Part Number: ep3c120f780c8nes
• Description: Cyclone Iii Device Family
• Manufacturer: Altera Corporation

Clock Networks and PLLs in Cyclone III Devices
6–32
Cyclone III Device Handbook, Volume 1
f
For more information on PLL software support in the Quartus II
software, see the altpll Megafunction User Guide.
Guidelines
Use the following guidelines to design with clock switchover in PLLs.
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Clock loss detection and automatic clock switchover requires that the
inclk0 and inclk1 frequencies be within 2X of each other. Failing
to meet this requirement causes the clkbad[0] and clkbad[1]
signals to function improperly.
When using manual clock switchover, the difference between
inclk0 and inclk1 can be more than 2X. However, differences in
frequency, phase, or both of the two clock sources will likely cause
the PLL to lose lock. Resetting the PLL ensures that the correct phase
relationships are maintained between input and output clocks.
Applications that require a clock switchover feature and a small
frequency drift should use a low-bandwidth PLL. The low-
bandwidth PLL reacts slower than a high-bandwidth PLL to
reference input clock changes. When the switchover happens, a low-
bandwidth PLL propagates the stopping of the clock to the output
slower than a high-bandwidth PLL. A low-bandwidth PLL filters out
jitter on the reference clock. However, be aware that the low-
bandwidth PLL also increases lock time.
After a switchover occurs, there may be a finite resynchronization
period for the PLL to lock onto a new clock. The exact amount of time
it takes for the PLL to re-lock is dependent on the PLL configuration.
If the phase relationship between the input clock to the PLL and
output clock from the PLL is important in your design, assert
areset for 10 ns after performing a clock switchover. Wait for the
locked signal (or gated lock) to go high before re-enabling the output
clocks from the PLL.
Figure 6–19
when the primary clock is lost and then increases as the VCO locks
on to the secondary clock. After the VCO locks on to the secondary
clock, some overshoot can occur (an over-frequency condition) in the
VCO frequency.
shows how the VCO frequency gradually decreases
Altera Corporation- Preliminary
March 2007