ep3c120f780c8nes Altera Corporation, ep3c120f780c8nes Datasheet - Page 134

• Manufacturer Part Number: ep3c120f780c8nes
• Description: Cyclone Iii Device Family
• Manufacturer: Altera Corporation

Clock Networks and PLLs in Cyclone III Devices
6–34
Cyclone III Device Handbook, Volume 1
For example, if f
and Φ
shift, a value which depends on the reference clock frequency and the
counter settings.
Coarse resolution phase shifts are implemented by delaying the start of
the counters for a predetermined number of counter clocks. You can
express coarse phase shift as:
Φ
Where C is the count value set for the counter delay time (this is the initial
setting in the PLL usage section of the compilation report in the
Quartus II software). If the initial value is 1, C – 1 = 0° phase shift.
Figure 6–20
resolution through VCO phase taps method. The eight phases from the
VCO are shown and labeled for reference. For this example, CLK0 is based
on the 0
one. The CLK1 signal is divided by four, two VCO clocks for high time
and two VCO clocks for low time. CLK1 is based on the 135° phase tap
from the VCO and has the C value for the counter set to one. The CLK1
signal is also divided by 4. In this case, the two clocks are offset by 3 Φ
CLK2 is based on the 0° phase from the VCO but has the C value for the
counter set to three. This creates a delay of 2 Φ
periods).
coarse
fine
= C-1/f
°
= 156.25 ps. The PLL operating frequency defines this phase
phase from the VCO and has the C value for the counter set to
shows an example of phase shift insertion using the fine
vco
REF
= (C-1)N/Mf
is 100 MHz, n = 1, and m = 8, then f
ref
Altera Corporation- Preliminary
coarse
(two complete VCO
VCO
= 800 MHz
March 2007
fine
.