ep3c120f780c8nes Altera Corporation, ep3c120f780c8nes Datasheet - Page 436

• Manufacturer Part Number: ep3c120f780c8nes
• Description: Cyclone Iii Device Family
• Manufacturer: Altera Corporation

Switching Characteristics
1–26
Cyclone III Handbook
Notes to
(1)
(2)
(3)
(4)
(5)
HSIODR
t
TCCS
Output jitter (peak to peak)
t
t
t
DUTY
RISE
FALL
LOCK
Table 1–32. Dedicated LVDS Transmitter Timing Specification
Pending silicon characterization.
Values for device speed grade -7 and -8 will be available after characterization.
The maximum data rate that complies with duty cycle distortion of 45–55%.
The maximum data rate when taking duty cycle in absolute ps into consideration that may not comply with
45–55% duty cycle distortion. If the downstream receiver can handle duty cycle distortion beyond the 45–55%
range, you may use the higher data rate values from this column. You can calculate the duty cycle distortion as a
percentage using the absolute ps value. For example, for a data rate of
640 Mbps (UI = 1625 ps) and a tDUTY of 250 ps, the duty cycle distortion is tDUTY/(UI*2) *100% = 250 ps/(1625
*2) * 100% = 7.7%, which gives you a duty cycle distortion of 42.3-57.7%.
Dedicated LVDS transmitter is only supported at output pin of Row I/O (Bank 1, 2, 5 and 6).
Table
Symbol
1–32:
20–80%
80–20%
Modes
x10
x8
x7
x4
x2
x1
(2)
Min
100
(1)
(1)
(1)
80
70
40
20
10
,
(5)
(Part 2 of 2)
-6 Speed Grade
Typ
(1)
(1)
Altera Corporation- Preliminary
Max
840
840
840
840
840
420
(3)
(1)
(1)
(1)
(1)
(1)
248
Max
(4)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
March 2007
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Unit
ms
ps
ps
ps
ps
%