ep3c120f780c8nes Altera Corporation, ep3c120f780c8nes Datasheet - Page 145

• Manufacturer Part Number: ep3c120f780c8nes
• Description: Cyclone Iii Device Family
• Manufacturer: Altera Corporation

Altera Corporation-Preliminary
March 2007
PHASECOUNTER
SELECT[2:0]
PHASEUPDOWN
PHASESTEP
SCANCLK
PHASEDONE
Table 6–14. Dynamic Phase Shifting Control Signals
Signal Name
Counter Select. Three bits decoded to select
either the M or one of the C counters for phase
adjustment. One address maps to select all
C counters. This signal is registered in the
PLL on the rising edge of
Selects dynamic phase shift direction; 1= UP;
0 = DOWN. Signal is registered in the PLL on
the rising edge of
Logic high enables dynamic phase shifting
Free running clock from core used in
combination with
enable/disable dynamic phase shifting. Shared
with
When asserted, it indicates to core-logic that
the phase adjustment is complete and PLL is
ready to act on a possible second adjustment
pulse. Asserts based on internal PLL timing.
De-asserts on rising edge of
SCANCLK
Table 6–14
shifting.
Table 6–15
PHASECOUNTERSELECT setting:
PHASECOUNTERSELECT [2]
for dynamic reconfiguration.
Description
PHASESTEP
SCANCLK
shows the control signals that are used for dynamic phase
shows the PLL counter selection based on the corresponding
0
0
0
0
1
1
1
SCANCLK
Table 6–15. Phase Counter Select Mapping
.
SCANCLK
to
.
.
[1]
0
0
1
1
0
0
1
Cyclone III Device Handbook, Volume 1
Logic array or I/O pins
Logic array or I/O pins
Logic array or I/O pins
GCLK or I/O pins
PLL reconfiguration
circuit
[0]
0
1
0
1
0
1
0
Source
All Output Counters
PLL Reconfiguration
C0 Counter
C1 Counter
C2 Counter
C3 Counter
C4 Counter
M Counter
Selects
PLL
reconfiguration
circuit
PLL
reconfiguration
circuit
PLL
reconfiguration
circuit
PLL
reconfiguration
circuit
Logic array or
I/O pins
Destination
6–45