ep3c120f780c8nes Altera Corporation, ep3c120f780c8nes Datasheet - Page 272

• Manufacturer Part Number: ep3c120f780c8nes
• Description: Cyclone Iii Device Family
• Manufacturer: Altera Corporation

Configuring Cyclone III Devices
10–36
Cyclone III Device Handbook, Volume 1
f
Upon power-up, the Cyclone III devices go through a POR. The POR
delay is dependent on the MSEL pin settings which correspond to the
configuration scheme that you select. Depending on the configuration
scheme, either a fast POR time or a standard POR time is available. The
fast POR time is 3ms < T
standard POR time is 50ms < T
ramp rate. During POR, the device resets, holds nSTATUS and
CONF_DONE low, and tri-states all user I/O pins. Once the device
successfully exits POR, all user I/O pins continue to be tri-stated. The
user I/O pins and dual-purpose I/O pins have weak pull-up resistors
which are always enabled (after POR) before and during configuration.
The value of the weak pull-up resistors on the I/O pins that are on before
and during configuration can be found in the DC and Switching
Characteristics chapter of the Cyclone III Device Handbook.
The three stages of the configuration cycle are reset, configuration, and
initialization. While nCONFIG or nSTATUS are low, the device is in reset.
After POR, the Cyclone III devices release nSTATUS, which is pulled high
by an external 10 KΩ pull-up resistor, and enters configuration mode.
1
The serial clock (DCLK) generated by the Cyclone III device controls the
entire configuration cycle and provides the timing for the parallel
interface. Cyclone III devices use an internal oscillator to generate DCLK.
Cyclone III devices use a 40 MHz oscillator for the AP configuration
scheme. The oscillator is the same oscillator used in the AS configuration
scheme and the active DCLK output frequency is as shown in
on page
After all configuration bits are received by the Cyclone III device, it
releases the open-drain CONF_DONE pin, which is pulled high by an
external 10 KΩ resistor. Initialization begins only after the CONF_DONE
signal reaches a logic high level. The CONF_DONE pin must have an
external 10 KΩ pull-up resistor in order for the device to initialize.
In Cyclone III devices, the initialization clock source is either the 10 MHz
(typical) internal oscillator (separate from the active serial internal
oscillator) or the optional CLKUSR pin. By default, the internal oscillator
is the clock source for initialization. If the internal oscillator is used, the
Cyclone III device provides itself with enough clock cycles for proper
initialization. The advantage of using the internal oscillator is you do not
10–17.
To begin configuration, power the V
the banks where the configuration and JTAG pins reside)
voltages to the appropriate voltage levels.
POR
< 9ms for fast configuration time. The
POR
< 200ms, which has a lower power
Altera Corporation-Preliminary
CCINT
, V
CCA
, and V
Table 10–7
March 2007
CCIO
(for