ep3c120f780c8nes Altera Corporation, ep3c120f780c8nes Datasheet - Page 233

• Manufacturer Part Number: ep3c120f780c8nes
• Description: Cyclone Iii Device Family
• Manufacturer: Altera Corporation

Conclusion
Document
Revision History
Altera Corporation-Preliminary
March 2007
March 2007 v1.0
Table 9–5. Document Revision History
Document
Date and
Version
f
system clock and generates the DQ signals during writes. You can use the
PLL reconfiguration feature to calibrate the read-capture phase shift to
balance the setup and hold margins.
1
For more information on the Cyclone III PLL, refer to the Clock Networks
and PLLs in Cyclone III Devices chapter in volume 1 of the Cyclone III
Device Handbook.
Cyclone III devices support DDR2 SDRAM, DDR SDRAM, and
QDRII SRAM external memory interfaces. The self-calibrating
ALTMEMPHY megafunction simplifies the implementation of data paths
for different memory interfaces and dynamically calibrates out the
process, voltage, and temperature variations in Cyclone III devices and
external memory devices without interrupting normal operation.
Cyclone III allows a transfer data rate between external memory
interfaces of up to 200 MHz/400 Mbps for DDR2 SDRAM,
167 MHz/333 Mbps for DDR SDRAM, and 167 MHz/667 Mbps for
QDRII SRAM devices. Cyclone III devices also offer dedicated write
DDIO registers to improve the output duty cycle and provide a better
write margin.
Table 9–5
The PLL is instantiated within the ALTMEMPHY megafunction.
All the outputs of the PLL are used when the ALTMEMPHY
megafunction is instantiated to interface with external
memories. For more information on usage of the PLL outputs by
the ALTMEMPHY megafunction, refer to the ALTMEMPHY
Megafunction User Guide found at the Altera web site at
www.altera.com.
shows the revision history for this document.
Changes Made
Initial Release
Cyclone III Device Handbook, Volume 1
Summary of Changes
Conclusion
9–19