mc68hc908ld64 Freescale Semiconductor, Inc, mc68hc908ld64 Datasheet - Page 108

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mc68hc908ld64

Manufacturer Part Number
mc68hc908ld64
Description
M68hc08 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Clock Generator Module (CGM)
8.6.3 PLL Programming Register (PPG)
Data Sheet
108
Address:
XLD — Crystal Loss Detect Bit
Bits [3:0] — Reserved for test
The PLL programming register contains the programming information for
the modulo feedback divider and the programming information for the
hardware configuration of the VCO.
Reset:
Read:
Write:
When the VCO output, CGMVCLK, is driving DCLK1, this read/write
bit indicates whether the crystal reference frequency is active or not.
To check the status of the crystal reference, the following procedure
should be followed:
1. Write a 1 to XLD.
2. Wait 4 × N cycles. (N is the VCO frequency multiplier, MUL[7:4].)
3. Read XLD.
The crystal loss detect function works only when the BCS bit is set,
selecting CGMVCLK to drive DCLK1. When BCS is clear, XLD always
reads as 0.
These bits enable test functions not available in user mode. To ensure
software portability from development systems to user applications,
software should write zeros to Bits [3:0] whenever writing to PBWC.
1 = Crystal reference is not active
0 = Crystal reference is active
$003A
MUL7
Bit 7
0
Figure 8-5. PLL Programming Register (PPG)
Clock Generator Module (CGM)
MUL6
6
1
MUL5
5
1
MUL4
4
0
VRS7
3
0
MC68HC908LD64
VRS6
Freescale Semiconductor
2
1
VRS5
1
1
Rev. 3.0
VRS4
Bit 0
0

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