mc68hc908ld64 Freescale Semiconductor, Inc, mc68hc908ld64 Datasheet - Page 124

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mc68hc908ld64

Manufacturer Part Number
mc68hc908ld64
Description
M68hc08 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
System Integration Module (SIM)
9.6.1 Interrupts
Data Sheet
124
INTERRUPT
I BIT
R/W
INTERRUPT
IDB
I BIT
IAB
R/W
IDB
IAB
MODULE
MODULE
DUMMY
DUMMY
SP – 4
SP
An interrupt temporarily changes the sequence of program execution to
respond to a particular event.
system interrupts.
Interrupts are latched, and arbitration is performed in the SIM at the start
of interrupt processing. The arbitration result is a constant that the CPU
uses to determine which vector to fetch. Once an interrupt is latched by
the SIM, no other interrupt can take precedence, regardless of priority,
until the latched interrupt is serviced (or the I bit is cleared).
At the beginning of an interrupt, the CPU saves the CPU register
contents on the stack and sets the interrupt mask (I bit) to prevent
additional interrupts. At the end of an interrupt, the RTI instruction
recovers the CPU register contents from the stack so that normal
processing can resume.
9-9
PC – 1[7:0] PC – 1[15:8]
CCR
shows interrupt recovery timing.
SP – 1
SP – 3
Figure 9-9. Interrupt Recovery
Figure 9-8
System Integration Module (SIM)
A
SP – 2
SP – 2
X
X
.
Interrupt Entry
SP – 3
SP – 1
Figure 9-8
PC – 1[15:8] PC – 1[7:0]
A
Figure 9-10
SP – 4
SP
CCR
shows interrupt entry timing.
VECT H
PC
OPCODE
V DATA H
flow charts the handling of
VECT L
PC + 1
MC68HC908LD64
OPERAND
V DATA L
Freescale Semiconductor
START ADDR
OPCODE
Figure
Rev. 3.0

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