mc68hc908ld64 Freescale Semiconductor, Inc, mc68hc908ld64 Datasheet - Page 261

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mc68hc908ld64

Manufacturer Part Number
mc68hc908ld64
Description
M68hc08 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
17.6.2 Sync Processor Input/Output Control Register (SPIOCR)
MC68HC908LD64
Freescale Semiconductor
Rev. 3.0
Figure 17-5. Sync Processor Input/Output Control Register (SPIOCR)
Address:
VPOL — Vsync Input Polarity
HPOL — Hsync Input Polarity
VSYNCS — VSYNC Input State
HSYNCS — HSYNC Input State
Reset:
Read: VSYNCS HSYNCS
Write:
This bit indicates the polarity of the VSYNC input, or the extracted
Vsync from a composite sync input (COMP=1). Reset clears this bit.
This bit indicates the polarity of the HSYNC input. This bit equals the
VPOL bit when the COMP bit is set. Reset clears this bit.
This read-only bit reflects the logical state of the VSYNC input.
This read-only bit reflects the logical state of the HSYNC input.
ATPOL
1 = Vsync is positive polarity
0 = Vsync is negative polarity
1 = Hsync is positive polarity
0 = Hsync is negative polarity
0
0
1
1
$0045
Bit 7
0
Table 17-4. ATPOL, VINVO, and HINVO setting
= Unimplemented
Sync Processor
6
0
VINVO / HINVO
COINV
0
1
0
1
5
0
R
4
Same polarity as sync input
Inverted polarity of sync input
Negative polarity sync output
Positive polarity sync output
R
R
3
Sync Outputs:
Sync Processor I/O Registers
VOUT/HOUT
= Reserved
R
2
BPOR
Sync Processor
1
0
Data Sheet
SOUT
Bit 0
0
261

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