mc68hc908ld64 Freescale Semiconductor, Inc, mc68hc908ld64 Datasheet - Page 279

• Manufacturer Part Number: mc68hc908ld64
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

18.7.3 OSD Data Registers (OSDDRH:OSDDRL)
MC68HC908LD64
Freescale Semiconductor
—
Rev. 3.0
Address:
Address:
DENDIF — OSD Display End Interrupt Flag
OSDD[15:0] — OSD RAM 16-Bit Data Buffer
Reset:
Reset:
Read:
Read:
Write:
Write:
This bit is set when the OSD has finished the row15 display; it is
cleared by writing a logic 0 to it. The DENDIF bit is designed for user
program to update the OSD RAM while not displaying OSD. Reset
clears this bit.
While OSD circuitry is displaying data from the display RAM, update
the display RAM (location specified by the row and column address
registers, OSDRAR and OSDCAR) by writing data to the high byte
register (OSDDRH) followed by the low byte register (OSDDRL). After
writing to the OSDDRL, the OSD buffer write ready bit (WRDY) will be
cleared. WRDY becomes set again when the OSD circuitry has
transferred the content of the OSD data registers to the display RAM.
Reset has no effect on these bits.
(See
1 = OSD has finished the row15 display
0 = No effect
OSDD15
OSDD7
$0063
$0062
18.6 OSD Screen Memory
Bit 7
Bit 7
Figure 18-7. OSD Data Register High (OSDDRH)
Figure 18-8. OSD Data Register Low (OSDDRL)
On-Screen Display (OSD)
OSDD14
OSDD6
6
6
OSDD13
OSDD5
5
5
OSDD12 OSDD11
OSDD4
Unaffected by reset
Unaffected by reset
4
4
Map.)
OSDD3
3
3
OSDD10
OSDD2
OSD Module I/O Registers
On-Screen Display (OSD)
2
2
OSDD1
OSDD9
1
1
Data Sheet
OSDD8
OSDD0
0
0
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