mc68hc908ld64 Freescale Semiconductor, Inc, mc68hc908ld64 Datasheet - Page 298

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mc68hc908ld64

Manufacturer Part Number
mc68hc908ld64
Description
M68hc08 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Input/Output (I/O) Ports
19.3.2 Data Direction Register A
Data Sheet
298
NOTE:
Address:
Data direction register A (DDRA) determines whether each port A pin is
an input or an output. Writing a logic 1 to a DDRA bit enables the output
buffer for the corresponding port A pin; a logic 0 disables the output
buffer.
DDRA[7:0] — Data Direction Register A Bits
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 19-4
Reset:
Read:
Write:
These read/write bits control port A data direction. Reset clears
DDRA[7:0], configuring all port A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
DDRA7
READ DDRA ($0004)
WRITE DDRA ($0004)
WRITE PTA ($0000)
READ PTA ($0000)
$0004
Bit 7
0
Figure 19-3. Data Direction Register A (DDRA)
shows the port A I/O logic.
Input/Output (I/O) Ports
DDRA6
6
0
Figure 19-4. Port A I/O Circuit
RESET
DDRA5
5
0
DDRA4
DDRAx
PTAx
4
0
DDRA3
3
0
MC68HC908LD64
DDRA2
Freescale Semiconductor
2
0
DDRA1
1
0
Rev. 3.0
DDRA0
Bit 0
0
PTAx

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