at75c220 ATMEL Corporation, at75c220 Datasheet - Page 11

• Manufacturer Part Number: at75c220
• Description: Smart Internet Appliance Processor Siap
• Manufacturer: ATMEL Corporation

Clocking
The AT75C220 mode register controls clock generation.
Oscillator and PLL
The AT75C220 uses an external 16 MHz crystal (XCLK)
and an on-chip PLL to generate the internal clocks. The
PLL generates a 240 MHz clock that is divided down to pro-
duce the ARM clock and Oak clock.
ARM System Clock
The ARM subsystem runs at 40 MHz.
Table 4. Clock Source and Frequency
Figure 5. AT75C220 Clocking
Boot Mode
The AT75C220 has an integrated 1-Kbyte ROM to support
the boot software. When the device is released from reset,
the ARM starts fetching from address 0x00000000. If the
RM flag in the SIAP-E mode register (SIAP_MD on page
12) is low, the internal boot ROM is mapped to the bottom
1K byte of the memory map. If RM is high, the bottom 16M
bytes of memory address will default to external memory
region 0.
If NDSRA/BOOTN is asserted on reset, the internal boot
ROM program is executed. The boot program reads data
from USART A and writes it to the Oak Program RAM (in
the ARM memory map whereas the Oak is in reset). The
downloaded software can then configure the various con-
Source
Crystal
PLL Output
ARM Clock
Oak Clock
10 pF
10 pF
16 MHz
XTAL
1 MΩ
XTALOUT
XTALIN
Oscillator
16 MHz
100 Ω
10 nF
PLL
. . 15
Frequency
XREF 240F
240 MHz
16 MHz
40 MHz
60 MHz
240 MHz
Oak System Clock
The Oak subsystem runs at 60MHz.
Other Clocks
The codec interfaces run from 800 kHz that is seperate
from the Oak clock.
The USARTs and timers operate from divided ARM clocks.
trol registers in the AT75C220 and its peripherals so as to
perform external memory accesses. This allows the Flash
to be written.
The boot ROM code:
• sets CTS active
• waits for approximately three seconds for the start of a
If the special header is not received, the AT75C220 boots
normally, i.e., from external memory at 0x00000000.
If the special header is received, the boot ROM enters the
code download process.
Flash download sequence from the USART.
. . 4
. . 6
60 MHz
Comment
External crystal
Crystal multiplied by 15
PLL divided by 6
PLL divided by 4
40 MHz
Generator
Phase
ARM Core
Clock
40 MHz
DSP Subsystem
Clock
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