at75c220 ATMEL Corporation, at75c220 Datasheet - Page 90

• Manufacturer Part Number: at75c220
• Description: Smart Internet Appliance Processor Siap
• Manufacturer: ATMEL Corporation

USART Channel Status Register
Name:
Access Type:Read-only
Reset Value: 0x18
•
•
•
•
•
•
•
•
•
90
RXRDY: Receiver Ready
TXRDY: Transmitter Ready
RXBRK: Break Received/End of Break
ENDRX: End-of-receive Transfer
ENDTX: End-of-transmit Transfer
OVRE: Overrun Error
FRAME: Framing Error
PARE: Parity Error
TIMEOUT: Receiver Time-out
0 = No complete character has been received since the last read of the US_RHR or the receiver is disabled.
1 = At least one complete character has been received and the US_RHR has not yet been read.
0 = US_THR contains a character waiting to be transferred to the Transmit Shift Register.
1 = US_THR is empty and there is no break request pending TSR availability.
Equal to zero when the USART is disabled or at reset. Transmitter enable command (in US_CR) sets this bit to one.
0 = No break received or end of break detected since the last reset status bits command in the Control Register.
1 = Break received or end of break detected since the last reset status bits command in the Control Register.
0 = The end-of-transfer signal from the PDC channel dedicated to the receiver is inactive.
1 = The end-of-transfer signal from the PDC channel dedicated to the receiver is active.
0 = The end-of-transfer signal from the PDC channel dedicated to the transmitter is inactive.
1 = The end-of-transfer signal from the PDC channel dedicated to the transmitter is active.
0 = No byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the
last reset status bits command.
1 = At least one byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted
since the last reset status bits command.
0 = No stop bit has been detected low since the last reset status bits command.
1 = At least one stop bit has been detected low since the last reset status bits command.
1 = At least one parity bit has been detected false (or a parity bit high in multi-drop mode) since the last reset status bit”
command.
0 = No parity bit has been detected false (or a parity bit high in multi-drop mode) since the last reset status bits
command.
0 = There has not been a time-out since the last start time-out command or the Time-out Register is 0.
1 = There has been a time-out since the last start time-out command.
PARE
31
23
15
–
–
–
7
US_CSR
FRAME
30
22
14
–
–
–
6
AT75C220
OVRE
29
21
13
–
–
–
5
ENDTX
28
20
12
–
–
–
4
ENDRX
27
19
11
–
–
–
3
RXBRK
DMSI
26
18
10
–
–
2
TXEMPTY
TXRDY
25
17
–
–
9
1
TIMEOUT
RXRDY
24
16
–
–
8
0