at75c220 ATMEL Corporation, at75c220 Datasheet - Page 81

• Manufacturer Part Number: at75c220
• Description: Smart Internet Appliance Processor Siap
• Manufacturer: ATMEL Corporation

Peripheral Data Controller
Each USART channel is closely connected to a corre-
sponding peripheral data controller channel. One is dedi-
cated to the receiver, the other is dedicated to the transmit-
ter.
Note:
The PDC channel is programmed using US_TPR and
US_TCR for the transmitter and US_RPR and US_RCR for
the receiver. The status of the PDC is given in US_CSR by
the ENDTX bit for the transmitter and by the ENDRX bit for
the receiver.
The pointer registers US_TPR and US_RPR are used to
store the address of the transmit or receive buffers. The
counter registers US_TCR and US_RCR are used to store
the size of these buffers.
The receiver data transfer is triggered by the RXRDY bit
and the transmitter data transfer is triggered by TXRDY.
When a transfer is performed, the counter is decremented
and the pointer is incremented. When the counter reaches
0, the status bit is set (ENDRX for the receiver, ENDTX for
the transmitter in US_CSR) and can be programmed to
generate an interrupt. Transfers are then disabled until a
new non-zero counter value is programmed.
Modem Control and Status Signals
NCTS: Clear to Send
When low, this indicates that the modem or data set is
ready to exchange data. The NCTS signal is a modem sta-
tus input whose conditions can be tested by the CPU
reading bit 4 (CTS) of the Modem Status Register. Bit 4 is
the complement of the NCTS signal. Bit 0 (DCTS) of the
Modem Status Register indicates whether the NCTS input
has changed state since the previous reading of the
Modem Status Register. NCTS has no effect on the
transmitter.
In FCM mode when the NCTS signal becomes inactive
high, the transmission of the current character will be com-
pleted then transmission stops.
Note:
NDCD: Data Carrier Detect
When low, this indicates that the data carrier has been
detected by the modem or data set. The NDCD signal is a
modem status input whose condition can be tested by the
CPU reading bit 7 (DCD) of the Modem Status Register. Bit
7 is the complement of the NDCD signal. Bit 3 (DDCD) of
the Modem Status Register indicates whether the NDCD
The PDC is disabled if 9-bit character length is selected
(MODE9 = 1) in US_MR.
Whenever the CTS bit of the Modem Status Register
changes state, an interrupt is generated if the Modem
Status Interrupt is enabled.
input pin has changed since the previous reading of the
Modem Status Register. NDCD has no effect on the
receiver.
Note:
NDSR: Data Set Ready
When low, this informs the modem or data set the USART
is ready to communicate. The NDSR signal is a modem
status input whose condition can be tested by the CPU
reading bit 5 (DSR) of the Modem Status Register. Bit 5 is
the complement of the NDSR signal. Bit 1 (DDSR of the
Modem Status Register) indicates whether the NDSR input
has changed state since the previous reading of the
Modem Status Register.
Note:
NDTR: Data Terminal Ready
When low, this informs the modem or data set that the
USART is ready to communicate. The NDTR output signal
can be set to active low by programming bit 0 (DTR) of the
Modem Control Register to a high level. A master reset
operation sets this signal to its inactive (high) state. Loop
mode operation holds this signal in its inactive state.
NRI: Ring Indicator
When low, this indicates that a telephone ringing signal has
been received by the modem or data set. The NRI signal is
a modem status input whose condition can be tested by the
CPU reading bit 6 (RI) of the Modem Status Register. Bit 6
is the complement of the NRI signal. Bit 2 (TERI) of the
Modem Status Register indicates whether the NRI input
signal has changed from a low to a high state since the pre-
vious reading of the Modem Status Register.
Note:
NRTS: Request to Send
When low, this informs the modem or data set that the
USART is ready to exchange data. The NRTS output signal
can be set to an active low by programming bit 1 (RTS) of
the Modem Control Register. A master reset operation sets
this signal to its inactive (high) state. In FCM mode when
the last stop bit of a character is transmitted and the Trans-
mit Holding Register is empty, the hardware sets NRTS
inactive high.
Note:
Whenever the DCD bit of the Modem Status Register
changes state, an interrupt is generated if the Modem
Status Interrupt is enabled.
Whenever the DSSR bit of the Modem Status Register
changes state, an interrupt is generated if the Modem
Status Interrupt is enabled.
Whenever the RI bit of the Modem Status Register
changes from a high to a low state, an interrupt is gener-
ated if the Modem Status Interrupt is enabled.
Modem control pins must be left high when not used.
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