at75c220 ATMEL Corporation, at75c220 Datasheet - Page 13

• Manufacturer Part Number: at75c220
• Description: Smart Internet Appliance Processor Siap
• Manufacturer: ATMEL Corporation

•
•
•
•
•
•
•
•
•
SA: Slow ARM Mode
LPCS: Low Power Clock Select
SW1: Software Reset 1
SW2: Software Reset 2
DBA: OAKA Debug Mode
CRA: CODECA Reset
IPOLTST: PLL Bias Adjustment
ICP: PLL Charge Pump Current
INDIV
0
0
1
1
On reset this field is low. In normal operating mode, if bit SA is set. The ARM clock is 34Mhz (i.e. the PLL value is
divided by 7). IF SA is not set the ARM clock is 40MHz (i..e the PLL divisor is 6). SA can be switched during low power
mode but should not be changed when LP is low.
This field is used to select a slower clock frequency for the ARM system clock as per the table below.
Writing a 1 to this bit forces the SIAP into reset with RM set to 0.
Writing a 1 to this bit forces the SIAP into reset with RM set to 1.
This flag resets low. To enter OAKA debug mode (specific pins are multiplexed out on functional pins), this bit should
be set.
This flag resets to active low so that the CODECA is held in reset. The CODECA is released from reset by asserting
this flag high.
This can be used to tune the PLL if the bias current is not correct after manufacture.
This can be used to tune the PLL if it does not function with the default current of 2.5 µA.
Input frequency range of PLL.
Bias Factor
I
=
LPCS
0
0
1
1
(
ICP
INDIV
0
1
0
1
+
1 )
=
×
(
0
1
0
1
15 IPOLTST
Oscillator Clock
2.5 µ A
–
Divisor
512
16
64
1
PLL Input Frequency Range
160 MHz to 250 MHz
80 MHz to 160 MHz
) 4 ⁄
40 MHz to 80 MHz
5 kHz to 40 MHz
ARM and Oak
System Clock
250 kHz
32 kHz
8 MHz
1 MHz
13