at75c220 ATMEL Corporation, at75c220 Datasheet - Page 130

• Manufacturer Part Number: at75c220
• Description: Smart Internet Appliance Processor Siap
• Manufacturer: ATMEL Corporation

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SPI Receive Data Register
Register Name:SP_RDR
Access Type:Read-only
Reset Value:0x0
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130
PCS: Peripheral Chip Select
DLYBCS: Delay Between Chip Selects
RD: Receive Data
PCS: Peripheral Chip Select Status
This field is only used if fixed peripheral select is active (PS=0).
If PCSDEC=0:
If PCSDEC=1:
This field defines the delay from NPCS inactive to the activation of another NPCS. The DLYBCS time guarantees non-
overlapping chip selects and solves bus contentions in case of peripherals with long data float times.
If DLYBCS equals zero, one SPI Master Clock period will be inserted by default.
Otherwise, the following equation determines the delay:
Data received by the SPI interface is stored in this register right-justified. Unused bits read zero.
In master mode only, these bits indicate the value on the NPCS pins at the end of a transfer. Otherwise, these bits read
as zero.
NPCS_to_SPCK_Delay
31
23
15
–
–
7
PCS = xxx0
PCS = xx01
PCS = x011
PCS = 0111
PCS = 1111
(x = don’t care)
NPCS[3:0] output signals = PCS
30
22
14
–
–
6
AT75C220
NPCS[3:0] = 1110
NPCS[3:0] = 1101
NPCS[3:0] = 1011
NPCS[3:0] = 0111
forbidden (no peripheral is selected)
=
DLYBCS SPI_Master_Clock_Period
29
21
13
–
–
5
×
28
20
12
–
–
4
RD
RD
27
19
11
–
3
26
18
10
–
2
PCS
25
17
–
9
1
24
16
–
8
0