at75c220 ATMEL Corporation, at75c220 Datasheet - Page 50

• Manufacturer Part Number: at75c220
• Description: Smart Internet Appliance Processor Siap
• Manufacturer: ATMEL Corporation

MAC Statistics Register Block
These registers reset to zero on a read and stick at all ones
when they count to their maximum value. They should be
read frequently enough to prevent loss of data.
Table 16. Statistics Register Block
50
Register Name
ETH_FRA
ETH_SCOL
ETH_MCOL
ETH_OK
ETH_SEQE
ETH_ALE
ETH_DTE
ETH_LCOL
ETH_ECOL
ETH_CSE
ETH_TUE
ETH_CDE
ETH_ELR
ETH_RJB
ETH_USF
ETH_SQEE
ETH_DRFC
AT75C220
Description
Frames transmitted OK. A 24-bit register counting the number of frames successfully transmitted.
Single collision frames. A 16-bit register counting the number of frames experiencing a single collision
before being transmitted and experiencing no carrier loss nor underrun.
Multiple collision frames. A 16-bit register counting the number of frames experiencing between two and
fifteen collisions prior to being transmitted (62 - 1518 bytes, no carrier loss, no underrun).
Frames received OK. A 24-bit register counting the number of good frames received, i.e. address
recognized. A good frame is of length 64 to 1518 bytes and has no FCS, alignment or code errors.
Frame checks sequence errors. An 8-bit register counting address-recognized frames with an integral
number of bytes long and that have bad CRC and 64 to 1518 bytes long.
Alignment errors. An 8-bit register counting frames that are:
- address recognized,
- not an integral number of bytes long
- have bad CRC when their length is truncated to an integral number of bytes
- between 64 and 1518 bytes in length.
Deferred transmission frames. A 16-bit register counting the number of frames experiencing deferral due to
carrier sense active on their first attempt at transmission (no underrun or collision).
Late collisions. An 8-bit register counting the number of frames that experience a collision after the slot
time (512 bits) has expired. No carrier loss or underrun. A late collision is counted twice, i.e., both as a
collision and a late collision.
Excessive collisions. An 8-bit register counting the number of frames that failed to be transmitted because
they experienced 16 collisions. (64 - 1518 bytes, no carrier loss or underrun)
Carrier sense errors. An 8-bit register counting the number of frames for which carrier sense was not
detected and maintained in half-duplex mode a slot time (512 bits) after the start of transmission (no
excessive collision).
Transmit errors. An 8-bit register counting the number of frames not transmitted due to a transmit DMA
underrun. If this register is incremented, then no other register is incremented.
Code errors. An 8-bit register counting the number of frames that are address recognized, had RXER
asserted during reception. If this counter is incremented, then no other counters are incremented.
Excessive length frames. An 8-bit register counting the number of frames received exceeding 1518 bytes
in length but that do not have either a CRC error, an alignment error or a code error.
Receive jabbers. An 8-bit register counting the number of frames received exceeding 1518 bytes in length
and having either a CRC error, an alignment error or a code error.
Undersize frames. An 8-bit register counting the number of frames received less than 64 bytes in length
but that do not have either a CRC error, an alignment error or a code error.
SQEE test errors. An 8-bit register counting the number of frames where COL was not asserted within a
slot time of TXEN being deasserted.
Discarded receive frames count. This 16-bit counter is incremented every time an address-recognized
frame is received but cannot be copied to memory because the receive buffer is available.
The statistics register block contains the registers found in
Table 16.