at75c220 ATMEL Corporation, at75c220 Datasheet - Page 18

• Manufacturer Part Number: at75c220
• Description: Smart Internet Appliance Processor Siap
• Manufacturer: ATMEL Corporation

valid longer than in standard read protocol due to the addi-
tional wait cycle that follows a write access.
Wait States
The SMC can automatically insert wait states. The different
types of wait states are:
• standard wait states
• data float wait states
• external wait states
• chip select change wait states
• early read wait states (see “Read Protocols” on page 17
•
Each chip select can be programmed to insert one or more
wait states during an access on the corresponding device.
This is done by setting the WSE field in the corresponding
SMC_CSR. The number of cycles to insert is programmed
in the NWS field in the same register. The correspondence
between the number of standard wait states programmed
and the number of cycles during which the write strobe
pulse is held low is found in Table 7. For each additional
wait state programmed, an additional cycle is added.
Table 7. Correspondence Wait States/Number of Cycles
•
Some memory devices are slow to release the external
bus. For such devices it is necessary to add wait states
(data float waits) after a read access before starting a write
access or a read access to a different external memory.
The Data Float Output Time (TDF) for each external mem-
or y de vi c e i s pr og ra mm ed in th e TDF fie ld of th e
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for details)
standard wait states
Data Float Wait State
Wait States
0
1
AT75C220
Cycles
1/2
1
SMC_CSR register for the corresponding chip select. The
value (0 - 7 clock cycles) indicates the number of data float
waits to be inserted and represents the time allowed for the
data output to go high impedance after the memory is dis-
abled.
The SMC keeps track of the programmed external data
float time even when it makes internal accesses to ensure
that the external memory system is not accessed while it is
still busy.
Internal memory accesses and consecutive accesses to
the same external memory do not have added data float
wait states.
When data float wait states are being used, the SMC pre-
vents the DMC or external master from accessing the
external data bus.
•
The NWAIT input can be used to add wait states at any
time NWAIT is active low and is detected on the rising edge
of the clock. If NWAIT is low at the rising edge of the clock,
the SMC adds a wait state and does not change the output
signals.
•
A chip select wait state is automatically inserted when con-
secutive accesses are made to two different external mem-
ories (if no wait states have already been inserted). If any
wait states have already been inserted (e.g., data float
wait), then none are added.
LCD Interface Mode
NCE3 can be configured for use with an external LCD con-
troller by setting the LCD bit in the SMC_CSR3 register.
Additionally, WSE must be set and NWS programmed with
a value of one or more.
In LCD mode, NCE3 is shortened by one-half clock cycle at
the leading and trailing edges, providing positive address
setup and hold. For read cycles, the data is latched in the
SMC as NCE3 is raised at the end of the access.
External Wait
Chip Select Change Wait States