at75c220 ATMEL Corporation, at75c220 Datasheet - Page 129

• Manufacturer Part Number: at75c220
• Description: Smart Internet Appliance Processor Siap
• Manufacturer: ATMEL Corporation

SPI Mode Register
Register Name:SP_MR
Access Type:Read/write
Reset Value:0x0
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MSTR: Master/Slave Mode
PS: Peripheral Select
PCSDEC: Chip Select Decode
MCK32: Clock Selection
LLB: Local Loopback Enable
0 = SPI is in slave mode.
1 = SPI is in master mode.
MSTR configures the SPI interface for either master or slave mode operation.
0 = Fixed peripheral select
1 = Variable peripheral select
0 = The chip selects are directly connected to a peripheral device.
1 = The four chip select lines are connected to a 4-to-16-bit decoder.
When PCSDEC equals one, up to one chip select signal can be generated with the four lines using an external
4-to-16-bit decoder.
The Chip Select Register defines the characteristics of the 16 chips selected according to the following rules:
SP_CSR0 defines peripheral chip select signals 0 to 3.
SP_CSR1 defines peripheral chip select signals 4 to 7.
SP_CSR2 defines peripheral chip select signals 8 to 11.
SP_CSR3 defines peripheral chip select signals 12 to 15.
0 = SPI master clock equals ACLK.
1 = SPI master clock equals ACLK/32.
0 = Local loopback path disabled.
1 = Local loopback path enabled.
LLB controls the local loopback on the data serializer for testing in master mode only.
LLB
31
23
15
–
–
7
30
22
14
–
–
6
–
29
21
13
–
–
5
–
28
20
12
–
–
4
–
DLYBCS
MCK32
27
19
11
–
3
PCSDEC
26
18
10
–
2
PCS
PS
25
17
9
–
1
MSTR
24
16
8
–
0
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