adau1781bcpz-rl Analog Devices, Inc., adau1781bcpz-rl Datasheet
adau1781bcpz-rl
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... One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 SigmaDSP Processing Core ADAU1781 2 C® or SPI protocols, and 2 S, left-justified, right- ADAU1781 AOUTL AOUTR LEFT DAC OUTPUT MIXER SPP RIGHT SPN DAC 2 I C/SPI CONTROL PORT ©2009 Analog Devices, Inc. All rights reserved. www.analog.com ...
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ADAU1781 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Specifications ..................................................................................... 4 Record Side Performance Specifications ................................... 4 Output Side Performance Specifications ................................... 6 Power Supply ...
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Speaker Driver Supply Trace (AVDD2) ................................... 47 Exposed Pad PCB Design .......................................................... 47 Control Register Map ..................................................................... 48 Clock Management, Internal Regulator, and PLL Control ... 49 Record Path Configuration ........................................................ 53 Serial Port Configuration ........................................................... 58 REVISION HISTORY 12/09—Revision ...
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ADAU1781 SPECIFICATIONS Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications. Supply voltages AVDD = AVDD1 = AVDD2 = I/O supply = 3.3 V, digital supply = 1.5 V, unless otherwise noted; ...
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Parameter Left/Right Microphone PGA Gain Range Left/Right Microphone PGA Mute Attenuation Interchannel Gain Mismatch Offset Error Gain Error Interchannel Isolation Power Supply Rejection Ratio DIFFERENTIAL MICROPHONE INPUT TO ADC PATH Full-Scale Input Voltage (0 dB) Dynamic Range With A-Weighted Filter ...
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ADAU1781 Parameter Dynamic Range With A-Weighted Filter (RMS) No Filter (RMS) Beep Input Mute Attenuation Offset Error Gain Error Interchannel Gain Mismatch Beep Input PGA Gain Range Beep Playback Mixer Gain Range Power Supply Rejection Ratio MICROPHONE BIAS Bias Voltage ...
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Parameter Dynamic Range With A-Weighted Filter (RMS) No Filter (RMS) Total Harmonic Distortion + Noise Signal-to-Noise Ratio With A-Weighted Filter (RMS) No Filter (RMS) Power Supply Rejection Ratio Gain Error Interchannel Gain Mismatch Offset Error DAC TO SPEAKER OUTPUT PATH ...
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ADAU1781 Parameter Total Harmonic Distortion + Noise Dynamic Range With A-Weighted Filter (RMS) No Filter (RMS) Signal-to-Noise Ratio With A-Weighted Filter (RMS) No Filter (RMS) Power Supply Rejection Ratio Differential Offset Error Mono Mixer Mute Attenuation, Beep to Mixer Path ...
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TYPICAL POWER MANAGEMENT MEASUREMENTS Master clock = 12.288 MHz, PLL is active in integer mode at a 256 × f −1 dBFS with a frequency of 1 kHz. Analog input and output are simultaneously active. Pseudo differential stereo input is ...
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ADAU1781 Parameter DAC INTERPOLATION FILTER Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay DIGITAL INPUT/OUTPUT SPECIFICATIONS −25°C < T < +85°C, IOVDD = 1. 3.63 V, unless otherwise specified. A Table 6. Parameter HIGH ...
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DIGITAL TIMING SPECIFICATIONS −25°C < T < +85°C, IOVDD = 1. 3.63 V, unless otherwise specified. A Table 7. Digital Timing Parameter t MIN MASTER CLOCK Duty Cycle 30 SERIAL PORT t 10 BIL t ...
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ADAU1781 Digital Timing Diagrams t BIH BCLK t BIL t LIS LRCLK t SIS DAC_SDATA LEFT-JUSTIFIED MSB MODE t SIH DAC_SDATA MODE DAC_SDATA RIGHT-JUSTIFIED MODE 8-BIT CLOCKS (24-BIT DATA) 12-BIT CLOCKS (20-BIT DATA) 14-BIT CLOCKS (18-BIT DATA) ...
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CLS t CLATCH CCPH CCLK CDATA t CDS COUT t t SCH SDA t SCL CLK DATA1/ DATA2 DATA1 t CCPL t CDH Figure 4. SPI Port Timing SDR SDF t SCR SCLH ...
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ADAU1781 ABSOLUTE MAXIMUM RATINGS Table 8. Parameter Power Supply (AVDD1 = AVDD2) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Operating Temperature Range (Case) Storage Temperature Range Stresses above those listed under Absolute ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 10. Pin Function Descriptions Pin No. Mnemonic Type 1 CM A_OUT 2 PDN A_IN 3 AGND1 PWR 4 AVDD1 PWR 5 DVDDOUT PWR 6 DGND PWR 7 GPIO D_IO 8 SCL/CCLK D_IN 9 SDA/COUT ...
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ADAU1781 Pin No. Mnemonic Type 18 MCKO D_OUT 19 AVDD2 PWR 20 SPN A_OUT SPP A_OUT 23 AGND2 PWR AOUTR A_OUT 26 AOUTL A_OUT 27 RMIC/RMICN/MICD2 A_IN 28 RMICP A_IN 29 LMICP A_IN 30 ...
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TYPICAL PERFORMANCE CHARACTERISTICS 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 0 0.1 0.2 0.3 0.4 0.5 0.6 FREQUENCY (NORMALIZED TO Figure 8. ADC Decimation Filter, 64× Oversampling, Normalized 0.04 0.02 0 –0.02 –0.04 ...
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ADAU1781 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 0 0.1 0.2 0.3 0.4 0.5 0.6 FREQUENCY (NORMALIZED TO Figure 14. DAC Interpolation Filter, 64× Oversampling, Normalized 0.20 0.15 0.10 0.05 0 –0.05 –0.10 ...
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SPEAKER OUTPUT POWER (mW) Figure 20. THD + N vs. Speaker Output Power, 8 Ω Load, 3.3 V Supply 0 –20 –40 –60 –80 –100 100 600 ...
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ADAU1781 SYSTEM BLOCK DIAGRAMS MICBIAS 0.1µF DIFFERENTIAL INPUT (LEFT) 10µF 49.9kΩ 10µF 49.9kΩ DIFFERENTIAL INPUT (RIGHT) 10µF 49.9kΩ 10µF 49.9kΩ 10µF EXTERNAL BEEP INPUT 49.9kΩ EXTERNAL 49.9kΩ MCLK SOURCE 2.2pF MCKO 49.9kΩ PDN IOVDD AVDD1 10µF 10µF 10µF AVDD2 47µF ...
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MICBIAS 0.1µF MICBIAS 0.1µF 2kΩ ANALOG LMIC/LMICN/MICD1 MIC 1 10µF 49.9kΩ LMICP 10µF MICBIAS 0.1µF 2kΩ ANALOG RMIC/RMICN/MICD2 MIC 2 10µF 49.9kΩ RMICP 10µF 10µF BEEP EXTERNAL BEEP INPUT 49.9kΩ MCKI EXTERNAL 49.9kΩ MCLK SOURCE 2.2pF MCKO 49.9kΩ MCKO PDN ...
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ADAU1781 MICBIAS 0.1µF SINGLE-ENDED STEREO INPUT 10µF 1kΩ 49.9kΩ 10µF 10µF 1kΩ 49.9kΩ 10µF 10µF EXTERNAL BEEP INPUT 49.9kΩ EXTERNAL 49.9kΩ MCLK SOURCE 2.2pF MCKO 49.9kΩ PDN IOVDD AVDD1 10µF 10µF 10µF AVDD2 47µF 0.1µF 0.1µF 0.1µF 0.1µF SPN SPP ...
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IOVDD 10µF 0.1µF MICBIAS 0.1µF STEREO DIGITAL LMIC/LMICN/MICD1 MIC INPUT LMICP 10µF ADAU1781 RMIC/RMICN/MICD2 R52 RMICP 10kΩ 10µF 10µF BEEP EXTERNAL BEEP INPUT 49.9kΩ MCKI EXTERNAL 49.9kΩ MCLK SOURCE 2.2pF MCKO 49.9kΩ MCKO PDN PDN Figure 25. System Block Diagram ...
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ADAU1781 THEORY OF OPERATION The ADAU1781 is a low power audio codec with an integrated, programmable SigmaDSP audio processing core all-in-one package that offers high quality audio, low power, small size, and many advanced features. The stereo ...
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STARTUP, INITIALIZATION, AND POWER This section details the procedure for setting up the ADAU1781 properly. Figure 26 provides an overview of how to initialize the IC. START YES ARE AVDD1 AND AVDD2 CAN AVDD1 AND AVDD2 SUPPLIED SEPARATELY? BE SIMULTANEOUSLY ...
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ADAU1781 CLOCK GENERATION AND MANAGEMENT The ADAU1781 uses a flexible clocking scheme that enables the use of many different input clock rates. The PLL can be bypassed or used, resulting in two different approaches to clock manage- ment. For more ...
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CLOCKING AND SAMPLING RATES PLL CONTROL f /X MCKI INPUT DIVIDE INTEGER, NUMERATOR DENOMINATOR CORE CLOCK The core clock divider generates a core clock either from the PLL or directly from MCLK and can be set ...
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ADAU1781 Table 14 and Table 15 list the sampling rate divisions for common base sampling rates. Table 14. Base Sampling Rate Divisions for f Base Sampling Frequency Sampling Rate Scaling kHz ...
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The ADC and DAC sampling rate can be set in Register 16407 (0x4017), Converter Control 0, Bits[2:0], converter sampling rate. The SigmaDSP core sampling rate and serial port sampling rate are similarly set in Register 16619 (0x40EB), SigmaDSP core frame ...
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ADAU1781 RECORD SIGNAL PATH BEEP PGA LMIC/LMICN/ MICD1 LEFT PGA LMICP ADC CM RMIC/RMICN/ MICD2 RIGHT PGA RMICP ADC CM Figure 30. Record Signal Path Diagram INPUT SIGNAL PATH The ADAU1781 can be configured for three types of microphone inputs: ...
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ANALOG-TO-DIGITAL CONVERTERS The ADAU1781 uses two 24-bit Σ-Δ analog-to-digital converters (ADCs) with selectable oversampling rates of either 64× or 128×. The full-scale input to the ADCs depends on AVDD1. At 3.3 V, the full-scale input level is 1.0 V rms. ...
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ADAU1781 PLAYBACK SIGNAL PATH LEFT PLAYBACK MIXER LEFT DAC LEFT PLAYBACK BEEP GAIN MONO PLAYBACK MONO BEEP GAIN PLAYBACK MIXER BEEP FROM RECORD PGA RIGHT PLAYBACK BEEP GAIN RIGHT DAC RIGHT PLAYBACK MIXER Figure 34. Playback Signal Path Diagram OUTPUT ...
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CONTROL PORTS The ADAU1781 can operate in one of two control modes: I control or SPI control. The ADAU1781 has both a 4-wire SPI control port and a 2-wire bus control port. Each can be used to ...
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ADAU1781 Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, the ADAU1781 immediately jumps to the idle condition. During a given ...
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I C Read and Write Operations Figure 39 shows the timing of a single-word write operation. Every ninth clock pulse, the ADAU1781 issues an acknowledge by pulling SDA low. Figure 40 shows the timing of a burst mode write ...
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ADAU1781 SPI PORT 2 By default, the ADAU1781 mode, but can be put into SPI control mode by pulling CLATCH low three times. The SPI port uses a 4-wire interface, consisting of CLATCH , CCLK, CDATA, ...
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CLATCH CCLK CDATA BYTE 0 Figure 43. SPI Write to ADAU1781 Clocking (Single-Write Mode) CLATCH CCLK CDATA BYTE 0 HIGH-Z COUT Figure 44. SPI Read from ADAU1781 Clocking (Single-Read Mode) BYTE 1 BYTE 1 BYTE 3 DATA Rev. 0| Page ...
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ADAU1781 SERIAL DATA INPUT/OUTPUT PORTS The flexible serial data input and output ports of the ADAU1781 can be set to accept or transmit data in 2-channel format 4-channel or 8-channel TDM stream to interface to external ADCs ...
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LEFT CHANNEL LRCLK BCLK SDATA MSB LRCLK LEFT CHANNEL BCLK MSB SDATA Figure 47. Left-Justified Mode—16 Bits to 24 Bits per Channel LEFT CHANNEL LRCLK BCLK SDATA MSB Figure 48. Right-Justified Mode—16 Bits to 24 Bits per Channel LRCLK BCLK ...
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ADAU1781 GENERAL-PURPOSE INPUT/OUTPUTS The serial data input/output pins are shared with the general- purpose input/output function. Each of these four pins can be set to only one function. The function of these pins is set in Register 16628 (0x40F4), serial ...
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DSP CORE SIGNAL PROCESSING The ADAU1781 is designed to provide all audio signal processing functions commonly used in stereo or mono low power record and playback systems. The signal processing flow is designed using the SigmaStudio™ software, which allows graphical ...
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ADAU1781 NUMERIC FORMATS DSP systems commonly use a standard numeric format. Fractional number systems are specified by an A.B format, where A is the number of bits to the left of the decimal point and B is the number of ...
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Figure 53. SigmaStudio Screen Shot Rev. 0| Page ADAU1781 ...
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ADAU1781 PROGRAM RAM, PARAMETER RAM, AND DATA RAM Table 27. RAM Map and Read/Write Modes Memory Size Parameter RAM 512 × 32 Program RAM 512 × 40 Table 27 shows the RAM map (the ADAU1781 register map is provided in ...
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Table 28. Parameter RAM Read/Write Format (Single Address) Byte 0 Byte 1 CHIP_ADR[6:0], R/W PARAM_ADR[15:8] Table 29. Parameter RAM Block Read/Write Format (Burst Mode) Byte 0 Byte 1 CHIP_ADR[6:0], R/W PARAM_ADR[15:8] Table 30. Program RAM Read/Write Format (Single Address) Byte ...
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ADAU1781 SOFTWARE SLEW When the values of signal processing parameters are changed abruptly in real time, they sometimes cause pop and click sounds to appear on the audio outputs. To avoid pops and clicks, some algorithms in SigmaStudio implement a ...
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APPLICATIONS INFORMATION POWER SUPPLY BYPASS CAPACITORS Each analog and digital power supply pin should be bypassed to its nearest appropriate ground pin with a single 100 nF capacitor. The connections to each side of the capacitor should be as short ...
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ADAU1781 CONTROL REGISTER MAP All registers except the PLL control register are 1-byte write and read registers. Table 33. Address Hex Decimal 0x4000 16384 0x4001 16385 0x4002 16386 0x4008 16392 0x4009 16393 0x400E 16398 0x400F 16399 0x4010 16400 0x4015 16405 ...
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CLOCK MANAGEMENT, INTERNAL REGULATOR, AND PLL CONTROL Register 16384 (0x4000), Clock Control The clock control register sets the clocking scheme for the ADAU1781. The system clock can be generated from either the PLL or directly from the MCKI (master clock ...
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ADAU1781 Register 16385 (0x4001), Regulator Control Bits[2:1], Regulator Output Level These bits set the regulated voltage output for the digital core, DVDDOUT. After the initialization sequence has completed, the regulator output is set to 1.4 V. The recommended regulator output ...
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Table 38. PLL Control Register Bits Description [47:40] Denominator MSB 00000000 and 00000000: M[15:8] and M[7: … 00000000 and 11111101: M[15:8] and M[7:0] = 125 … 11111111 and 11111111: M[15:8] and M[7:0] = 65,535 [39:32] Denominator LSB 00000000 ...
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ADAU1781 Table 39. Fractional PLL Parameter Settings for f MCLK Input (MHz) Input Divider ( 14.4 1 19.2 1 19.68 1 19.8 1 Table 40. Fractional PLL Parameter Settings for f MCLK Input (MHz) Input Divider ...
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RECORD PATH CONFIGURATION Register 16392 (0x4008), Digital Microphone and Analog Beep Control This register controls the digital microphone settings and the analog beep input gain. Bits[5:4], Digital Microphone Enable These bits control the enable function for the stereo digital microphones. ...
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ADAU1781 Register 16393 (0x4009), Record Power Management This register manages the power consumption for the record path. In particular, the current distribution for the mixer boosts, ADC, front-end mixer, and PGAs can be set in one of four modes. The ...
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Register 16398 (0x400E), Record Gain Left PGA The record gain left PGA control register controls the left channel input PGA. This register configures the input for either differ- ential or single-ended signals and sets the left channel input recording volume. ...
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ADAU1781 Register 16399 (0x400F), Record Gain Right PGA The record gain right PGA control register controls the right channel input PGA. This register configures the input for either differential or single-ended signals and sets the right channel input recording volume. ...
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Register 16400 (0x4010), Microphone Bias Control and Beep Enable Bit 4, Beep Input Enable This bit enables the beep signal, which is input to the BEEP pin. Setting this bit to 0 mutes the beep signal for all output paths. ...
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ADAU1781 SERIAL PORT CONFIGURATION Register 16405 (0x4015), Serial Port Control 0 Bit 5, LRCLK Mode This bit sets the serial port frame clock (LRCLK) as either a 50% duty cycle waveform or a pulse synchronization waveform. When in slave mode, ...
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BCLK POLARITY LRCLK BCLK SDATA LRCLK BCLK SDATA LRCLK POLARITY LRCLK L LRCLK LRCLK STEREO CHANNELS TDM 4 CHANNELS 1 TDM 8 CHANNELS 1 2 LRCLK FIRST PAIR TDM 4 CHANNELS 1 FIRST PAIR 1 2 TDM 8 CHANNELS Figure ...
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ADAU1781 Register 16406 (0x4016), Serial Port Control 1 Bits[7:5], Number of Bit Clock Cycles per Frame These bits set the number of BCLK cycles contained in one LRCLK period. The frequency of BCLK is calculated as the number of bit ...
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LRCLK BCLK LRCLK BCLK ...
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ADAU1781 LRCLK BCLK SERIAL DATA M (DELAY BY 0) SERIAL DATA M (DELAY BY 1) SERIAL DATA M (DELAY BY 8) LRCLK BCLK ...
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AUDIO CONVERTER CONFIGURATION Register 16407 (0x4017), Converter Control 0 Bits[6:5], On-Chip DAC Data Selection in TDM Mode These bits set the position of the DAC input channels on a TDM stream. In TDM 4 mode, valid settings are first pair ...
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ADAU1781 LRCLK TDM 4 CHANNELS FIRST PAIR LEFT TDM 8 CHANNELS LRCLK TDM 4 CHANNELS FIRST PAIR TDM 8 CHANNELS LRCLK FIRST PAIR TDM 8 CHANNELS f 1/ LRCLK FIRST PAIR LEFT RIGHT SECOND PAIR RIGHT Figure 70. Example of ...
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Register 16408 (0x4018), Converter Control 1 Bits[1:0], On-Chip ADC Data Selection in TDM Mode These bits set the position of the ADC output channels on a TDM stream. In TDM 4 mode, valid settings are first pair or second pair. ...
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ADAU1781 Register 16409 (0x4019), ADC Control Bit 6, Invert Input Polarity This bit enables an optional polarity inverter in the ADC path, which is an amplifier with a gain of −1, representing a 180° phase shift. Bit 5, High-Pass Filter ...
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Register 16410 (0x401A), Left ADC Attenuator Bits[7:0], Left ADC Digital Attenuator These bits control a 256-step, logarithmically spaced volume control from −95.625 dB, in increments of 0.375 dB. When a new value is entered into this register, ...
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ADAU1781 PLAYBACK PATH CONFIGURATION Register 16412 (0x401C), Playback Mixer Left Control Bit 5, Left DAC Mute This bit mutes the left DAC output. It does not have any slew and is updated immediately when the register write has been completed. ...
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Register 16415 (0x401F), Playback Mono Mixer Control Bit 7, Left DAC Mute This bit mutes the left DAC output, but does not power down the DAC. Use of this bit does not result in power savings. Bit 6, Right DAC ...
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ADAU1781 Register 16421 (0x4025), Left Line Output Mute Bit 1, Left Line Output Mute This bit mutes the left line output. It does not have any effect on the speaker outputs. Table 57. Left Line Output Mute Register Bits Description ...
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Register 16423 (0x4027), Playback Speaker Output Control Bits[7:6], Speaker Output Gain Control These bits control the gain of the speaker output. In general, this parameter should be tuned at a system level, set once during system initialization and not altered ...
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ADAU1781 Register 16425 (0x4029), Playback Power Management This register controls the unity current supplied to each functional block described. Within the functional blocks, the current can be multiplied. Normal operation has a base current of 2.5 μA, enhanced performance has ...
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Register 16426 (0x402A), DAC Control Bits[7:6], Mono Mode These bits control the output mode of the DAC. Setting these bits to 00 outputs two distinct channels, left and right. Setting these bits to 01 outputs the left input channel on ...
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ADAU1781 Register 16427 (0x402B), Left DAC Attenuator Bits[7:0], Left DAC Digital Attenuator These bits control a 256-step, logarithmically spaced volume control from −95.625 dB, in increments of 0.375 dB. When a new value is entered into this ...
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PAD CONFIGURATION Figure 73 shows a block diagram of the pad design for the GPIO/serial port and communications port pins. OUTPUT ENABLE OUTPUT PULL-UP ENABLE (CONTROLS PMOS) DEBOUNCE ENABLE DATA IN DEBOUNCE WEAK PULL-UP ENABLE WEAK PULL-DOWN ENABLE DRIVE STRENGTH ...
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ADAU1781 Register 16429 (0x402D), Serial Port Pad Control 0 Bits[7:6], ADC_SDATA Pad Pull-Up/Pull-Down These bits enable or disable a weak pull-up or pull-down device on the pad. The effective resistance of the pull-up or pull-down is nominally 240 kΩ. Bits[5:4], ...
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Register 16430 (0x402E), Serial Port Pad Control 1 Bit 3, ADC_SDATA Pin Drive Strength This bit sets the drive strength of the ADC_SDATA pin. Low mode yields 2 mA when IOVDD = 3 0.75 mA when IOVDD = ...
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ADAU1781 Register 16431 (0x402F), Communication Port Pad Control 0 Bits[7:6], CDATA Pad Pull-Up/Pull-Down These bits enable or disable a weak pull-up or pull-down device on the pad. The effective resistance of the pull-up or pull-down is nominally 240 kΩ. Bits[5:4], ...
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Register 16432 (0x4030), Communication Port Pad Control 1 Bit 3, CDATA Pin Drive Strength This bit sets the drive strength of the CDATA pin. Low mode yields 2 mA when IOVDD = 3 0.75 mA when IOVDD = ...
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ADAU1781 Register 16433 (0x4031), MCKO Control Bit 2, MCKO Pin Drive Strength This bit sets the drive strength of the MCKO pin. Low mode yields 2 mA when IOVDD = 3 0.75 mA when IOVDD = 1.8 V. ...
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DIGITAL SUBSYSTEM CONFIGURATION Register 16512 (0x4080), Digital Power-Down 0 Bit 7, ADC Engine Setting this bit to 0 disables the ADCs and the digital micro- phone inputs. Bit 6, Memory Controller Setting this bit to 0 disables all memory access, ...
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ADAU1781 Register 16513 (0x4081), Digital Power-Down 1 Bit 3, Output Precharge The output precharge system allows the outputs to be biased before they are enabled and prevents pops or clicks from appearing on the output. This bit should be set ...
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Register 16582 to Register 16586 (0x40C6 to 0x40CA), GPIO Pin Control Bits[3:0], GPIO Pin Function The GPIO pin control register sets the functionality of each GPIO pin as depicted in Table 73. GPIO0 to GPIO3 use the same pins as ...
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ADAU1781 Register 16617 and Register 16618 (0x40E9 and 0x40EA), Nonmodulo These registers set the boundary for the nonmodulo RAM space used by the SigmaDSP core. An appropriate value is automatically loaded to this register during initialization. It should not be ...
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Register 16626 (0x40F2), Serial Input Route Control Bits[3:0], Input Routing These bits select which serial data input channels are routed to the DACs (see Figure 74). Table 77. Serial Input Route Control Register Bits Description [7:4] Reserved [3:0] Input routing ...
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ADAU1781 Register 16627 (0x40F3), Serial Output Route Control Bits[3:0], Output Routing These bits select where the ADC outputs are routed in the serial data stream (see Figure 74). Table 78. Serial Output Route Control Register Bits Description [7:4] Reserved [3:0] ...
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Register 16628 (0x40F4), Serial Data/GPIO Pin Configuration Bits[3:0], GPIO[0:3] The serial data/GPIO pin configuration register controls the functionality of the serial data port pins. If the bits in this register are set to 1, then the GPIO[0:3] pins become GPIO ...
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... Temperature Range ADAU1781BCPZ 1 −25°C to +85°C 1 ADAU1781BCPZ-RL −25°C to +85°C 1 ADAU1781BCPZ-RL7 −25°C to +85°C 1 EVAL-ADAU1781Z RoHS Compliant Part. 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I ...