adau1781bcpz-rl Analog Devices, Inc., adau1781bcpz-rl Datasheet - Page 29

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adau1781bcpz-rl

Manufacturer Part Number
adau1781bcpz-rl
Description
Low Noise Stereo Codec With Sigmadsp Processing Core
Manufacturer
Analog Devices, Inc.
Datasheet
The ADC and DAC sampling rate can be set in Register 16407
(0x4017), Converter Control 0, Bits[2:0], converter sampling
rate. The SigmaDSP core sampling rate and serial port sampling
rate are similarly set in Register 16619 (0x40EB), SigmaDSP
core frame rate, Bits[3:0], SigmaDSP core frame rate, and
Register 16632 (0x40F8), serial port sampling rate, Bits[2:0],
serial port control sampling rate, respectively.
Table 18 and Table 19 depict example sampling rate settings.
The (1 × 256) case is the base sampling rate.
Rev. 0| Page 29 of 88
Table 18. Sampling Rates for 256 × 48 kHz Core Clock
Core Clock
12.288 MHz
Table 19. Sampling Rates for 256 × 44.1 kHz Core Clock
Core Clock
11.2896 MHz
Sampling Rate Divider
(1 × 256)
(6 × 256)
(4 × 256)
(3 × 256)
(2 × 256)
(1.5 × 256)
(0.5 × 256)
Sampling Rate Divider
(1 × 256)
(6 × 256)
(4 × 256)
(3 × 256)
(2 × 256)
(1.5 × 256)
(0.5 × 256)
Sampling Rate
48 kHz
8 kHz
12 kHz
16 kHz
24 kHz
32 kHz
96 kHz
Sampling Rate
44.1 kHz
7.35 kHz
11.025 kHz
14.7 kHz
22.05 kHz
29.4 kHz
88.2 kHz
ADAU1781

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