adau1781bcpz-rl Analog Devices, Inc., adau1781bcpz-rl Datasheet - Page 51

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adau1781bcpz-rl

Manufacturer Part Number
adau1781bcpz-rl
Description
Low Noise Stereo Codec With Sigmadsp Processing Core
Manufacturer
Analog Devices, Inc.
Datasheet
Table 38. PLL Control Register
Bits
[47:40]
[39:32]
[31:24]
[23:16]
15
[14:11]
[10:9]
8
[7:2]
1
0
Description
Denominator MSB
00000000 and 00000000: M[15:8] and M[7:0] = 0
00000000 and 11111101: M[15:8] and M[7:0] = 125
11111111 and 11111111: M[15:8] and M[7:0] = 65,535
Denominator LSB
00000000 and 00000000: M[15:8] and M[7:0] = 0
00000000 and 11111101: M[15:8] and M[7:0] = 125
11111111 and 11111111: M[15:8] and M[7:0] = 65,535
Numerator MSB
00000000 and 00000000: N[15:8] and N[7:0] = 0
00000000 and 00001100: N[15:8] and N[7:0] = 12
11111111 and 11111111: N[15:8] and N[7:0] = 65,535
Numerator LSB
00000000 and 00000000: N[15:8] and N[7:0] = 0
00000000 and 00001100: N[15:8] and N[7:0] = 12
11111111 and 11111111: N[15:8] and N[7:0] = 65,535
Reserved
Integer
0010: R = 2
0011: R = 3
0100: R = 4
0101: R = 5
0110: R = 6
0111: R = 7
1000: R = 8
Input divider
00: no division
01: divide by X = 2
10: divide by X = 3
11: divide by X = 4
PLL type
0: integer-N
1: fractional
Reserved
PLL lock (read only)
0: unlocked
1: locked (sticky bit)
PLL enable
0: disabled
1: enabled
Rev. 0| Page 51 of 88
Default
00000111
01010011
00000010
10000111
0011
00
1
1
1
ADAU1781

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