adau1781bcpz-rl Analog Devices, Inc., adau1781bcpz-rl Datasheet - Page 40
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adau1781bcpz-rl
Manufacturer Part Number
adau1781bcpz-rl
Description
Low Noise Stereo Codec With Sigmadsp Processing Core
Manufacturer
Analog Devices, Inc.
Datasheet
1.ADAU1781BCPZ-RL.pdf
(88 pages)
- Current page: 40 of 88
- Download datasheet (938Kb)
ADAU1781
GENERAL-PURPOSE INPUT/OUTPUTS
The serial data input/output pins are shared with the general-
purpose input/output function. Each of these four pins can be
set to only one function. The function of these pins is set in
Register 16628 (0x40F4), serial data/GPIO pin configuration.
The GPIO pins can be used as either inputs or outputs. These pins
are readable and can be set either through the control interface
or directly by the SigmaDSP core. When set as inputs, these
pins can be used with push-button switches or rotary encoders
to control SigmaDSP core program settings. Digital outputs can
be used to drive LEDs or external logic to indicate the status of
internal signals and control other devices. Examples of this use
include indicating signal overload, signal present, and button
press confirmation.
When set as an output, each pin can typically drive 2 mA. This
is enough current to directly drive some high efficiency LEDs.
Standard LEDs require about 20 mA of current and can be driven
Rev. 0 | Page 40 of 88
from a GPIO output with an external transistor or buffer. Because
of issues that may arise from simultaneously driving or sinking a
large current on many pins, care should be taken in the application
design to avoid connecting high efficiency LEDs directly to many
or all of the GPIO pins. If many LEDs are required, use an external
driver. When the GPIO pins are set as open-collector outputs,
they should be pulled up to a maximum voltage of what is set
on IOVDD.
The configuration of the GPIO functions is set up in Register 16582
to Register 16586 (0x40C6 to 0x40CA), GPIO pin control.
GPIOs Set from Control Port
The GPIO pins can also be set to be directly controlled from the
I
memory locations are enabled for the GPIO pin settings
(see Table 74). The physical settings on the GPIO pins mirror
the settings of the LSB of these 4-byte-wide memory locations.
2
C/SPI control port. When the pins are set into this mode, five
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