adau1781bcpz-rl Analog Devices, Inc., adau1781bcpz-rl Datasheet - Page 84

• Manufacturer Part Number: adau1781bcpz-rl
• Description: Low Noise Stereo Codec With Sigmadsp Processing Core
• Manufacturer: Analog Devices, Inc.

ADAU1781
Register 16617 and Register 16618 (0x40E9 and 0x40EA),
Nonmodulo
These registers set the boundary for the nonmodulo RAM space
used by the SigmaDSP core. An appropriate value is
automatically loaded to this register during initialization. It
should not be modified for any reason.
Table 75. Nonmodulo Registers
Bits
[31:0]
Table 76. SigmaDSP Core Frame Rate Register
Bits
[7:4]
[3:0]
Description
Reserved
Description
Reserved
SigmaDSP core frame rate
0000: f
0001: f
0010: f
0011: f
0100: f
0101: f
0110: f
0111: serial data input rate
1000: serial data output rate
1001: f
1010: none
…
1111: none
S
S
S
S
S
S
S
S
/1.5 (32 kHz)
/2 (24 kHz)
/3 (16 kHz)
/4 (12 kHz)
/6 (8 kHz)
× 2 (96 kHz)
(48 kHz)
× 4 (192 kHz)
Rev. 0 | Page 84 of 88
Register 16619 (0x40EB), SigmaDSP Core Frame Rate
Bits[3:0], SigmaDSP Core Frame Rate
These bits set the frequency of the frame start pulse, which is
delivered to the SigmaDSP core to begin processing on each audio
frame. It effectively determines the sample rate of audio in the
SigmaDSP core. This register should always be set to none at least
one frame prior to disabling Register 16630 (0x40F6), SigmaDSP
core run, Bit 0, SigmaDSP core run, to allow the SigmaDSP core
to finish processing the current frame before halting.
Default
0000