adau1781bcpz-rl Analog Devices, Inc., adau1781bcpz-rl Datasheet - Page 66

• Manufacturer Part Number: adau1781bcpz-rl
• Description: Low Noise Stereo Codec With Sigmadsp Processing Core
• Manufacturer: Analog Devices, Inc.

ADAU1781
Register 16409 (0x4019), ADC Control
Bit 6, Invert Input Polarity
This bit enables an optional polarity inverter in the ADC path,
which is an amplifier with a gain of −1, representing a 180°
phase shift.
Bit 5, High-Pass Filter Select
This bit enables an optional high-pass filter in the ADC path,
with a cutoff frequency of 2 Hz when f
frequency scales linearly with f
Bit 4, Digital Microphone Data Polarity Swap
This bit inverts the polarity of valid data states for the digital
microphone data stream. A typical PDM microphone can drive
its data output pin either high or low, not both. This bit must be
configured accordingly to recognize a valid output state of the
microphone. The default is negative, meaning that a digital
logic low signal is recognized by the ADAU1781 as a pulse in
the PDM signal.
Table 50. ADC Control Register
Bits
7
6
5
4
3
2
[1:0]
Description
Reserved
Invert input polarity
0: normal
1: inverted
High-pass filter select
0: disabled
1: enabled
Digital microphone data polarity swap
0: negative
1: positive
Digital microphone channel swap
0: standard mode
1: swapped mode
Digital microphone input select
0: digital microphone input off
1: select digital microphone input, ADCs off
ADC enable
00: both off
01: left on
10: right on
11: both on
S
.
S
= 48 kHz. The cutoff
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Bit 3, Digital Microphone Channel Swap
This bit allows the left and right channels of the digital microphone
input to swap. Standard mode is the left channel on the rising
edge and the right channel on the falling edge. Swapped mode is
the right channel on the rising edge and the left channel on the
falling edge.
Bit 2, Digital Microphone Input Select
This bit must be enabled to use the digital microphone inputs.
When this bit is asserted, the on-chip ADCs are off, BCLK is
the master at 128 × f
left and right channels interleaved. This bit must be disabled to
use the ADCs.
Bits[1:0], ADC Enable
These bits must be configured to use the ADCs. ADC channels
can be enabled or disabled individually.
S
, and ADC_SDATA is expected to have the
Default
0
0
0
0
0
00