adau1781bcpz-rl Analog Devices, Inc., adau1781bcpz-rl Datasheet - Page 60

• Manufacturer Part Number: adau1781bcpz-rl
• Description: Low Noise Stereo Codec With Sigmadsp Processing Core
• Manufacturer: Analog Devices, Inc.

ADAU1781
Register 16406 (0x4016), Serial Port Control 1
Bits[7:5], Number of Bit Clock Cycles per Frame
These bits set the number of BCLK cycles contained in one
LRCLK period. The frequency of BCLK is calculated as the
number of bit clock cycles per frame times the sample rate of
the serial port in hertz. Figure 63 and Figure 64 show examples
of different settings for these bits.
Bit 4, ADC Channel Position in TDM
This register sets the order of the ADC channels when output on
the serial output port. A setting of 0 puts the left channel first in its
respective TDM channel pair. A setting of 1 puts the right channel
first in its respective TDM channel pair. This bit should be set in
conjunction with Register 16408 (0x4018), Converter Control 1,
Bits[1:0], on-chip ADC data selection in TDM mode, to select
where the data should appear in the TDM stream. Figure 65 shows
a setting of 0, and Figure 66 shows a setting of 1.
Bit 3, DAC Channel Position in TDM
This register sets the order of the DAC channels when output on
the serial output port. A setting of 0 puts the left channel first in its
respective TDM channel pair. A setting of 1 puts the right channel
first in its respective TDM channel pair. This bit should be set in
conjunction with Register 16407 (0x4017), Converter Control 0,
Bits[6:5], on-chip DAC data selection in TDM mode, to select
where the data should appear in the TDM stream. Figure 65
shows a setting of 0, and Figure 66 shows a setting of 1.
Table 47. Serial Port Control 1 Register
Bits
[7:5]
4
3
2
[1:0]
Description
Number of bit clock cycles per frame
000: 64
001: 32
010: 48
011: 128
100: 256
101: reserved
110: reserved
111: reserved
ADC channel position in TDM
0: left first
1: right first
DAC channel position in TDM
0: left first
1: right first
MSB position
0: MSB first
1: MSB last
Data delay from LRCLK edge
00: 1 BCLK cycle
01: 0 BCLK cycles
10: 8 BCLK cycles
11: 16 BCLK cycles
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Bit 2, MSB Position
This bit sets the bit-level endianness (or bit order) of the data
stream. A setting of 0 results in a big-endian order, with the MSB
coming first in the stream and the LSB coming last. A setting of 1
results in a little-endian order, with the LSB coming first in the
stream and the MSB coming last. Figure 67 shows examples of
the two settings with a 24-bit audio stream in an MSB delay-by-0
configuration. In Figure 67, M stands for MSB, and L stands for LSB.
Bits[1:0], Data Delay from LRCLK Edge
These bits set the delay between the LRCLK edge and the first
data bit in the stream. The I
cycle. Examples of different data delay settings are shown
in Figure 68, with a 64 BCLK cycle per frame, 24-bit audio data,
big-endian bit order configuration. In Figure 68, M represents
the most significant bit of the audio channel’s data, and L represents
the least significant bit.
The first example setting (delay by 0) in Figure 68 represents a left-
justified mode because the least significant bit aligns with the
beginning of the audio frame. The third example setting (delay
by 8) represents a right-justified mode because the least significant
bit aligns with the end of the audio frame. A delay-by-16 setting
would not be valid in this mode because the audio data would
exceed the boundaries of the frame clock period.
Figure 69 shows an example of delay by 16 for a 16-bit audio
stream with 64 BCLK cycles per frame.
2
S standard is a delay of one BCLK
Default
000
0
0
0
00