adau1781bcpz-rl Analog Devices, Inc., adau1781bcpz-rl Datasheet - Page 15

• Manufacturer Part Number: adau1781bcpz-rl
• Description: Low Noise Stereo Codec With Sigmadsp Processing Core
• Manufacturer: Analog Devices, Inc.

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 10. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Mnemonic
CM
PDN
AGND1
AVDD1
DVDDOUT
DGND
GPIO
SCL/CCLK
SDA/COUT
ADDR0/CDATA
ADDR1/CLATCH
IOVDD
DAC_SDATA/GPIO0
ADC_SDATA/GPIO1
BCLK/GPIO2
LRCLK/GPIO3
MCKI
Type
A_OUT
A_IN
PWR
PWR
PWR
PWR
D_IO
D_IN
D_IO
D_IN
D_IN
PWR
D_IO
D_IO
D_IO
D_IO
D_IN
1
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD IS CONNECTED INTERNALLY TO THE
ADAU1781 GROUNDS. FOR INCREASED RELIABILITY OF THE
SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS
RECOMMENDED THAT THE PAD BE SOLDERED TO THE
GROUND PLANE.
Description
VDD/2 V Common-Mode Reference. A 10 μF to 47 μF decoupling capacitor should be
connected between this pin and ground to reduce crosstalk between the ADCs and DACs.
The material of the capacitors is not critical. This pin can be used to bias external analog
circuits, as long as they are not drawing current from CM (for example, the noninverting
input of an op amp).
Power-Down. Setting this pin to 0 powers down the chip. Resides in AVDD1 domain.
Analog Ground.
Analog Power Supply. Should be equivalent to AVDD2.
Digital Core Supply Decoupling Point. The digital supply is generated from an on-board
regulator and does not require an external supply. DVDDOUT should be decoupled to DGND
with a 100 nF capacitor.
Digital Ground.
Dedicated General-Purpose Input/Output.
I
I
I
I
Supply for Digital Input and Output Pins. The digital output pins are supplied from IOVDD,
which sets the highest allowed input voltage for the digital input pins. The current draw of
this pin is variable because it is dependent on the loads of the digital outputs. IOVDD should
be decoupled to DGND with a 100 nF capacitor.
DAC Serial Input Data/General-Purpose Input and Output.
Serial Data Port Bit Clock/General-Purpose Input and Output.
Serial Data Port Frame Clock/General-Purpose Input and Output.
Master Clock Input.
ADC Serial Output Data/General-Purpose Input and Output.
2
2
2
2
SCL/CCLK
DVDDOUT
C Clock/SPI Clock.
C Data/SPI Data Output.
C Address 0/SPI Data Input.
C Address 1/SPI Latch Signal.
AGND1
AVDD1
DGND
Figure 7. 32-Lead LFCSP Pin Configuration
GPIO
PDN
CM
1
2
3
4
5
6
7
8
Rev. 0| Page 15 of 88
ADAU1781
(Not to Scale)
PIN 1
INDICATOR
TOP VIEW
24 NC
23 AGND2
22 SPP
21 NC
20 SPN
19 AVDD2
18 MCKO
17 MCKI
ADAU1781