adau1781bcpz-rl Analog Devices, Inc., adau1781bcpz-rl Datasheet - Page 87

• Manufacturer Part Number: adau1781bcpz-rl
• Description: Low Noise Stereo Codec With Sigmadsp Processing Core
• Manufacturer: Analog Devices, Inc.

Register 16628 (0x40F4), Serial Data/GPIO Pin
Configuration
Bits[3:0], GPIO[0:3]
The serial data/GPIO pin configuration register controls the
functionality of the serial data port pins. If the bits in this
register are set to 1, then the GPIO[0:3] pins become GPIO
interfaces to the SigmaDSP core. If these bits are set to 0, they
remain LRCLK, BCLK, or serial port data pins, respectively.
Register 16630 (0x40F6), SigmaDSP Core Run
Bit 0, SigmaDSP Core Run
This bit, in conjunction with the SigmaDSP core frame rate,
initiates audio processing in the SigmaDSP core. When this bit is
enabled, the program counter begins to increment when a new
frame of audio data is input to the SigmaDSP core. When this bit is
disabled, the SigmaDSP core goes into standby mode.
Table 79. Serial Data/GPIO Pin Configuration Register
Bits
[7:4]
3
2
1
0
Table 80. SigmaDSP Core Run Register
Bits
[7:1]
0
Table 81. Serial Port Sampling Rate Register
Bits
[7:3]
[2:0]
Description
Reserved
SigmaDSP core run
0: SigmaDSP core standby
1: run the SigmaDSP core
Description
Reserved
Serial port control sampling rate
000: f
001: f
010: f
011: f
100: f
101: f
110: f
111: reserved
Description
Reserved
GPIO0
0: LRCLK
1: GPIO enabled
GPIO1
0: BCLK
1: GPIO enabled
GPIO2
0: serial data output
1: GPIO enabled
GPIO3
0: serial data input
1: GPIO enabled
S
S
S
S
S
S
S
/1 (48 kHz)
/6 (8 kHz)
/4 (12 kHz)
/3 (16 kHz)
/2 (24 kHz)
/1.5 (32 kHz)
/0.5 (96 kHz)
Rev. 0| Page 87 of 88
Before going into standby mode, the following sequence must
be performed:
1.
2.
3.
When reenabling the SigmaDSP core run bit, the following
sequence must be followed:
1.
2.
Register 16632 (0x40F8), Serial Port Sampling Rate
Bits[2:0], Serial Port Control Sampling Rate
These bits set the serial port sampling rate as a function of the
audio sampling rate, f
sampling rate, SigmaDSP core sampling rate, and ADC and
DAC sampling rates should be equal.
Set the SigmaDSP core frame rate in Register 16619 to
0x7F (none).
Wait 3 ms.
Set the SigmaDSP core run bit in Register 16630 to 0x00.
Set the SigmaDSP core frame rate in Register 16619 to an
appropriate value.
Set the SigmaDSP core run bit in Register 16630 to 0x01.
S
. In most applications, the serial port
Default
0
0
0
0
Default
0
Default
000
ADAU1781