adau1781bcpz-rl Analog Devices, Inc., adau1781bcpz-rl Datasheet - Page 27

• Manufacturer Part Number: adau1781bcpz-rl
• Description: Low Noise Stereo Codec With Sigmadsp Processing Core
• Manufacturer: Analog Devices, Inc.

CLOCKING AND SAMPLING RATES
CORE CLOCK
The core clock divider generates a core clock either from the
PLL or directly from MCLK and can be set in Register 16384
(0x4000), clock control.
The core clock is always in 256 × f
quencies must correspond to a value listed in Table 12, where f
is the base sampling frequency. PLL outputs are always in 1024
× f
core clock divider to f/4 when using the PLL.
Table 12. Core Clock Frequency Dividers
Input Clock Rate
256 × f
512 × f
768 × f
1024 × f
Clocks for the converters, the serial ports, and the SigmaDSP
core are derived from the core clock. The core clock can be
derived directly from MCLK, or it can be generated by the
PLL. Register 16384 (0x4000), clock control, Bit 3, clock source
select, determines the clock source.
Bits[2:1], input master clock frequency, should be set according
to the expected input clock rate selected by Bit 3, clock source
select. The clock source select value also determines the core
clock rate and the base sampling frequency, f
S
mode, and the clock control register automatically sets the
MCKI
S
S
S
S
INPUT DIVIDE
1, 2, 3, 4
f
/X
Core Clock Divider
f/1
f/2
f/3
f/4
PLL CONTROL
S
INTEGER, NUMERATOR,
mode. Direct MCLK fre-
DENOMINATOR
f × (R + N/M)
S
.
Core Clock
256 × f
Figure 28. Clock Routing Diagram
S
WHEN PLL CLOCK SOURCE SELECTED
AUTOMATICALLY SET TO 1024 ×
Rev. 0| Page 27 of 88
S
CLOCK FREQUENCY
CLOCK CONTROL
768 ×
256 ×
INPUT MASTER
f
f
S
S
, 1024 ×
, 512 ×
For example, if the input to Bit 3 = 49.152 MHz (from PLL),
then Bits[2:1] = 1024 × f
Table 13. Clock Control Register (Register 16384, 0x4000)
Bits
3
[2:1]
0
SAMPLING RATES
The ADCs, DACs, and serial port share a common sampling
rate that is set in Register 16407 (0x4017), Converter Control 0.
Bits[2:0], converter sampling rate, set the sampling rate as a ratio of
the base sampling frequency. The SigmaDSP core sampling rate
is set in Register 16619 (0x40EB), SigmaDSP core frame rate,
Bits[3:0], SigmaDSP core frame rate, and the serial port
sampling rate is set in Register 16632 (0x40F8), serial port
sampling rate, Bits[2:0], serial port control sampling rate.
It is strongly recommended that the sampling rates for the
converters, serial ports, and SigmaDSP core be set to the same
value, unless appropriate compensation filtering is done within
the SigmaDSP core.
f
f
S
S
f
S
,
= 49.152 MHz/1024 = 48 kHz
Bit Name
Clock source select
Input master clock
frequency
Core clock enable
CLOCK
f
CORE
S
0.5, 1, 1.5, 2, 3, 4, 6
0.5, 1, 1.5, 2, 3, 4, 6
0.5, 1, 1.5, 2, 3, 4, 6
SAMPLING RATE
SAMPLING RATE
SOUND ENGINE
SERIAL PORT
FRAME RATE
CONVERTER
S
; therefore,
f
f
f
S
S
S
/
/
/
Settings
0: direct from MCKI pin (default)
1: PLL clock
00: 256 × f
01: 512 × f
10: 768 × f
11: 1024 × f
0: core clock disabled (default)
1: core clock enabled
ADCs
S
S
S
INPUT/OUTPUT
SERIAL DATA
(default)
S
ENGINE
SOUND
PORTS
ADAU1781
DACs