aduc7062 Analog Devices, Inc., aduc7062 Datasheet - Page 33

• Manufacturer Part Number: aduc7062
• Description: Low-power, Precision Analog Microcontroller, Dual ?-? Adcs, Flash/ee, Arm7tdmi
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
•
ADC Comparator and Accumulator
Every primary ADC result can be compared to a preset
threshold level (ADC0TH) as configured via ADCCFG[4:3]. An
MCU interrupt is generated if the absolute (sign independent)
value of the ADC result is greater than the preprogrammed
comparator threshold level. An extended function of this
comparator function allows user code to configure a threshold
counter (ADC0THV) to monitor the number of Primary ADC
results that have occurred above or below the preset threshold
level. Again, an ADC interrupt is generated when the threshold
counter reaches a preset value (ADC0TCL).
Finally, a 32-bit accumulator (ADC0ACC) function can be
configured (ADCCFG[6:5]) allowing the Primary ADC to add
(or subtract) multiple Primary ADC sample results. User code
can read the accumulated value directly (ADC0ACC) without
any further software processing.
ADC MMR Interface
The ADCs are controlled and configured through a number of
MMRs that are described in detail in the following sections.
In response to an ADC interrupt, user code should interrogate
the ADCSTA MMR to determine the source of the interrupt.
Table 32. ADCSTA MMR Bit Designations
Bit
15
14
13
12
11 to 7
6
5
ence source in power saving mode. This bit has no effect
on power consumption if an external reference is used.
ADCMDE[7]—Clearing this bit further reduces power
consumption by reducing the frequency of the ADC clock.
Name
ADCCALSTA
ADC1CERR
ADC0CERR
ADC0ATHEX
Description
ADC Calibration Status.
Not Used.
Auxiliary ADC Conversion Error.
Primary ADC Conversion Error.
Not Used. These bits are reserved for future functionality and should not be monitored by user code.
ADC0 Accumulator Comparator Threshold Exceeded.
This bit is set when the ADC0 Accumulator value in ADC0ACC has exceeded the threshold value programmed in
the ADC0 Comparator Threshold register, ADCOATH.
This bit is cleared when the value in ADC0ATH does not exceed the value in ADC0ATH
Not Used. This bit is reserved for future functionality and should not be monitored by user code.
This bit is set automatically in hardware to indicate that a primary ADC conversion overrange or underrange has
occurred. The conversion result is clamped to negative full scale (underrange error) or positive full scale
(overrange error) in this case.
This bit is cleared when a valid (in-range) conversion result is written to the ADC0DAT register.
This bit is set automatically in hardware to indicate an ADC calibration cycle has been completed.
This bit is cleared after ADCMDE is written to.
This bit is reserved for future functionality
This bit is set automatically in hardware to indicate that an auxiliary ADC conversion overrange or underrange
has occurred. The conversion result is clamped to negative full scale (underrange error) or positive full scale
(overrange error) in this case.
This bit is cleared when a valid (in-range) voltage conversion result is written to the ADC1DAT register.
Rev. PrA | Page 33 of 100
Each ADC interrupt source can be individually masked via the
ADCMSKI MMR described in Table 32.
All primary ADC result ready bits are cleared by a read of the
ADC0DAT MMR. If the primary channel ADC is not enabled,
all ADC result ready bits are cleared by a read of the ADC1DAT
MMR. To ensure that primary ADC and auxiliary ADC
conversion data are synchronous, user code should first read
the ADC1DAT MMR and then the ADC0DAT MMR. New
ADC conversion results are not written to the ADCxDAT
MMRs unless the respective ADC result ready bits are first
cleared. The only exception to this rule is the data conversion
result updates when the ARM core is powered down. In this
mode, ADCxDAT registers always contain the most recent
ADC conversion result even though the ready bits have not
been cleared.
ADC Status Register
Name:
Address:
Default value:
Access:
Function:
ADuC7060/ADuC7061/ADuC7062
ADCSTA
0xFFFF0500
0x0000
Read only
This read-only register holds general status
information related to the mode of operation
or current status of the ADuC7060/ADuC7061/
ADuC7062 ADCs.