aduc7062 Analog Devices, Inc., aduc7062 Datasheet - Page 80

• Manufacturer Part Number: aduc7062
• Description: Low-power, Precision Analog Microcontroller, Dual ?-? Adcs, Flash/ee, Arm7tdmi
• Manufacturer: Analog Devices, Inc.

ADuC7060/ADuC7061/ADuC7062
SERIAL CLOCK GENERATION
The I
transfer. The master channel can be configured to operate in
fast mode (400 kHz) or standard mode (100 kHz).
The bit rate is defined in the I2CDIV MMR as follows:
where:
f
DIVH = the high period of the clock.
DIVL = the low period of the clock.
Thus, for 100 kHz operation
and for 400 kHz
The I2CDIV register corresponds to DIVH:DIVL.
I
Slave Mode
In slave mode, the registers I2CID0, I2CID1, I2CID2, and
I2CID3 contain the device IDs. The device compares the four
I2CIDx registers to the address byte received from the bus
master. To be correctly addressed, the 7 MSBs of either ID
register must be identical to that of the 7 MSBs of the first
received address byte. The LSB of the ID registers (the transfer
direction bit) is ignored in the process of address recognition.
I
I
Name:
Address:
Default value:
Access:
Function:
Table 90. I2CMCON MMR Bit Designations
Bit
15 to 9
8
7
6
UCLK
2
2
2
C Master Registers
C BUS ADDRESSES
C Master Control Register
DIVH = DIVL = 0x33
DIVH = 0x0A, DIVL = 0x0F
= clock before the clock divider.
2
f
C master in the system generates the serial clock for a
SERIAL
Name
I2CMCENI
I2CNACKENI
I2CALENI
CLOCK
=
I2CMCON
0xFFFF0900
0x0000
Read/write
This 16-bit MMR configures I
2 (
+
DIVH
Description
Reserved. These bits are reserved and should not be written to.
I
Set this bit to enable an interrupt on detecting a Stop condition on the I
Clear this interrupt source.
I
Set this bit to enable interrupts when the I
Clear this interrupt source.
I
Set this bit to enable interrupts when the I
Clear this interrupt source.
2
2
2
C transmission complete interrupt enable bit.
C no acknowledge (NACK) received Interrupt enable bit.
C Arbitration Lost Interrupt Enable bit.
f
UCLK
)
+
(2
+
DIVL
)
2
C peripheral in master mode.
Rev. PrA | Page 80 of 100
2
2
C master receives a no acknowledge (NACK).
C master has lost in trying to gain control of the I
The ADuC7060 also supports 10-bit addressing mode. When
Bit 1 of I2CSCON (ADR10EN bit) is set to 1, then one 10-bit
address is supported in slave mode and is stored in registers
I2CID0 and I2CID1. The 10-bit address is derived as follows:
I2CID0[0] is the read/write bit and is not part of the I
address.
I2CID0[7:1] = Address Bits[6:0].
I2CID1[2:0] = Address Bits[9:7].
I2CID1[7:3] must be set to 11110b
Master Mode
In master mode, the I2CADR0 register is programmed with the
I
In 7-bit address mode, I2CADR0[7:1] are set to the device
address. I2CADR0[0] is the read/write bit.
In 10-bit address mode, the 10-bit address is created as follows:
I2CADR0[7:3] must be set to 11110b.
I2CADR0[2:1] = Address Bits[9:8].
I2CADR1[7:0] = Address Bits[7:0].
I2CADR0[0] is the read/write bit.
I
The I
these are master related only, 7 are slave related only, and there
are 2 MMRs common to both master and slave modes.
2
2
C address of the device.
C REGISTERS
2
C peripheral interface consists overall of 19 MMRs. 10 of
Preliminary Technical Data
2
C bus.
2
C bus.
2
C