aduc7062 Analog Devices, Inc., aduc7062 Datasheet - Page 86

• Manufacturer Part Number: aduc7062
• Description: Low-power, Precision Analog Microcontroller, Dual ?-? Adcs, Flash/ee, Arm7tdmi
• Manufacturer: Analog Devices, Inc.

ADuC7060/ADuC7061/ADuC7062
I
Name:
Address:
Default value:
Access:
Function:
Table 98. I2CSSTA MMR Bit Designations
Bit
15
14
13
12 to 11
10
9 to 8
7
6
5
2
C Slave Status Register
Name
I2CSTA
I2CID[1:0]
I2CSS
I2CGCID[1:0]
I2CGC
I2CSBUSY
I2CSNA
I2CREPS
I2CSSTA
0xFFFF092C
0x0000
Read/write
This 16-bit MMR is the I
Description
Reserved bit.
This bit is set to 1 if:
A) A Start Condition followed by a matching address is detected.
B) It is also set if a Start byte (0x01) is received.
C) If General Calls are enabled and a General Call code of (0x00) is received.
This bit is cleared on receiving a Stop condition
This bit is set to 1 if a Repeated Start condition is detected.
This bit is cleared on receiving a Stop condition
I
[00] = Received address matches I2CID0,
[01] = Received address matches I2CID1
[10] = Received address matches I2CID2
[11] = Received address matches I2CID3
I
This bit is set to 1 when a Stop condition is detected after a previous Start and matching address.
When the I2CSSENI bit in I2CSCON is set, an interrupt will be generated.
This bit is cleared by reading this register.
I
[00] = No general Call received.
[01] = General Call Reset & Program Address.
[10] = General Program Address.
[11] = General Call matching alternative ID
Note: These bits will not be cleared by a General Call reset command.
Clear these bits by writing a 1 to the I2CGCCLR bit in I2CSCON.
I
This bit is set to 1 if the slave receives a General Call command of any type.
If the command received was a Reset command, then all registers will return to their default state.
If the command received was a Hardware General Call, the Rx FIFO holds the 2
Can be compared with the I2CALT register.
Clear this bit by writing a 1 to the I2CGCCLR bit in I2CSCON.
I
Set to 1 when the Slave receives a Start condition
Cleared by hardware if:
I
This bit is set to 1 when the Slave responds to a bus address with a no acknowledge. This bit is asserted under the
following conditions:
This bit is cleared in all other conditions.
a) The received address does not match any of the I2CSIDx registers
b) The slave device receives a stop condition.
c) If a Repeated Start address doesn’t match any of the I2CSIDx registers
2
2
2
2
2
2
a) If no acknowledge was returned because there was no data in the Tx FIFO
b) If the I2CNACKEN bit was set in the I2CSCON register.
C Address matching register. These bits indicate which I2CIDx register matches the received address.
C Stop Condition after Start detected bit.
C General Call ID bits
C General Call Status bit
C Slave Busy Status bit
C Slave NO ACKNOWLEDGE (NACK) Data bit
2
C status register in slave mode.
Rev. PrA | Page 86 of 100
Preliminary Technical Data
nd
byte of the command and this