aduc7062 Analog Devices, Inc., aduc7062 Datasheet - Page 50

• Manufacturer Part Number: aduc7062
• Description: Low-power, Precision Analog Microcontroller, Dual ?-? Adcs, Flash/ee, Arm7tdmi
• Manufacturer: Analog Devices, Inc.

ADuC7060/ADuC7061/ADuC7062
DAC PERIPHERALS
DAC
The ADuC706x incorporates a 12-bit voltage output DAC on-
chip. The DAC has a rail-to-rail voltage output buffer capable of
driving 5 kΩ/100 pF.
The DAC has four selectable ranges:
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•
•
•
The maximum signal range is 0 V to AVDD.
Table 58. DAC0CON MMR Bit Designations
Bit
15:10
9
8
7
6
5
4
3
2
1:0
DAC0DAT Register
Name:
Address:
Default
Value:
Access:
Function:
0 V to VREF (internal band gap 1.2 V reference)
VREF− to VREF+
EXT_REF2− to EXT_REF2+
0 V to AVDD
DAC0DAT
0xFFFF0604
0x00000000
Read/Write
This 32-bit MMR contains the DAC output value.
Value
11
10
01
00
Name
DACPD
DACBUFLP
OPAMP
DACBUFBYPASS
DACCLK
/DACCLR
DACMODE
RATE
DAC Range bits
Reserved.
Set to 1 to enable DAC in 16-bit interpolation mode.
Description
Set to 1 to power down DAC output (DAC output is tristated).
Clear this bit to enable the DAC.
Set to 1 to place the DAC output buffer in low power mode. See DAC Output
Buffer Section for further details on electrical specifications.
Clear this bit to enable the DAC buffer.
Set to 1 to place the DAC output buffer in op-amp mode.
Clear this bit to enable the DAC output buffer for normal DAC operation.
Set to 1 to bypass the output buffer and send the DAC output directly to the
output pin.
Clear this bit to buffer the DAC output.
Set to 1 to update the DAC on the negative edge of HCLK.
Set to 0 to update the DAC on the negative edge of Timer1. This mode is ideally
suited for waveform generation where the next value in the waveform is written
to DAC0DAT at regular intervals of Timer1.
Set to 0 to clear the DAC output and DACDATto 0. Writing to this bit has an
immediate effect on the DAC output.
Set to 0 to enable DAC in normal 12-bit mode.
Used with Interpolation Mode.
Set to 1 to configure the interpolation clock as UCLK/16.
Set to 0 to configure the interpolation clock as UCLK/32.
0 V to AV
EXT_REF2- to EXT_REF2+
VREF− to VREF+
0 V to V
Rev. PrA | Page 50 of 100
REF
DD
(1.2 V) Range. (Internal reference source.)
Range.
Op Amp Mode
As an option, the DAC may be disabled and its output buffer
used as an op amp.
MMR INTERFACE
The DAC is configurable through a control register and a data
register.
DAC0CON Register
Name:
Address:
Default value:
Access:
Table 59. DAC0DAT MMR Bit Designations
Bit
31:28
27:16
15:12
11:0
Description
Reserved.
12-Bit Data for DAC0.
Extra four 4 bits used in interpolation mode.
Reserved.
Preliminary Technical Data
DAC0CON
0xFFFF0600
0x0200
Read/write