aduc7062 Analog Devices, Inc., aduc7062 Datasheet - Page 35

• Manufacturer Part Number: aduc7062
• Description: Low-power, Precision Analog Microcontroller, Dual ?-? Adcs, Flash/ee, Arm7tdmi
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
ADC Mode Register
Name:
Address:
Default Value:
Access:
Function:
Table 34. ADCMDE MMR Bit Designations
Bit
7
6
5
4 to 3
2 to 0
Name
ADCCLKSEL
ADCLPMREFSEL
ADCLPMCFG[1:0]
ADCMD[2:0]
ADCMDE
0xFFFF0508
0x00
Read/write
The ADC mode MMR is an 8-bit register that configures the mode of operation of the ADC subsystem.
Description
Set this bit to 1 to enable ADCCLK = 4 MHz. This bit should be set for normal ADC operation
Clear this bit to enable ADCCLK = 131 kHz. This bit should be set for low power ADC operation
Not Used. These bits are reserved for future functionality and should not be monitored by user code.
Low Power Mode Reference Select.
ADC Power Mode Configuration.
ADC Operation Mode Configuration.
0, 0, 0 = ADC power-down mode. All ADC circuits and the input amplifier are powered down.
0, 0, 1 = ADC continuous conversion mode. In this mode, any enabled ADC continuously converts at a
frequency equal to f
0, 1, 0 = ADC Single conversion mode. In this mode, any enabled ADC performs a single conversion. The ADC
enters idle mode when the single shot conversion is complete. A single conversion takes two to three ADC clock
cycles depending on the chop mode.
0, 1, 1 = ADC idle mode. In this mode, the ADC is fully powered on but is held in reset. The part enters this
mode after calibration.
1, 0, 0 = ADC self-offset calibration. In this mode, an offset calibration is performed on any enabled ADC using
an internally generated 0 V. The calibration is carried out at the user programmed ADC settings; therefore, as
with a normal single ADC conversion, it takes two to three ADC conversion cycles before a fully settled
calibration result is ready. The calibration result is automatically written to the ADCxOF MMR of the respective
ADC. The ADC returns to idle mode and the calibration and conversion ready status bits are set at the end of an
offset calibration cycle.
Note: Always use ADC0 for single-ended self-calibration cycles on the primary ADC. Always use ADC0/ADC1
when self-calibrating for a differential input to the primary ADC.
1, 0, 1 = Reserved.
1, 1, 0 = ADC system zero-scale calibration. In this mode, a zero-scale calibration is performed on enabled ADC
channels against an external zero-scale voltage driven at the ADC input pins. To do this, the channel should be
shorted externally.
1, 1, 1 = ADC system full-scale calibration. In this mode, a full-scale calibration is performed on enabled ADC
channels against an external full-scale voltage driven at the ADC input pins. The ADCxGN register is updated
after a full-scale calibration sequence.
This bit is set to 1 to enable the high power precision voltage reference in low power mode . This increases
current consumption.
This bit is set to 0 to enable the low power voltage reference in low power mode (default).
This bit has no effect if the ADC is in normal mode.
0, 0 = ADC normal mode. If enabled, the ADC operates with normal current consumption yielding optimum
electrical performance.
0, 1 = ADC low power mode.
1, 0 = ADC normal mode, same as [0,0].
1, 1 = ADC low power plus mode (low power mode + PGA off ).
ADC
. RDY must be cleared to enable new data to be written to ADC0DAT/ADC1DAT
Rev. PrA | Page 35 of 100
ADuC7060/ADuC7061/ADuC7062