aduc7062 Analog Devices, Inc., aduc7062 Datasheet - Page 94

• Manufacturer Part Number: aduc7062
• Description: Low-power, Precision Analog Microcontroller, Dual ?-? Adcs, Flash/ee, Arm7tdmi
• Manufacturer: Analog Devices, Inc.

ADuC7060/ADuC7061/ADuC7062
GENERAL-PURPOSE I/O
The ADuC706x features up to sixteen general-purpose
bidirectional input/output (GPIO) pins. In general, many of the
GPIO pins have multiple functions that are configurable by user
code. By default, the GPIO pins are configured in GPIO mode.
All GPIO pins have an internal pull-up resistor with a drive
capability of 1.6 mA.
All I/O pins are 3.3 V tolerant, meaning the GPIOs support an
input voltage of 3.3 V.
When the ADuC706x enters a power-saving mode, the GPIO
pins retain their state.
The GPIO pins are grouped into three port busses. Table 102
lists all the GPIO pins and their alternative functions. A GPIO
pin alternative function can be selected by writing to the correct
bits of the GPxCON register.
Table 102. GPIO Pin Function Descriptions
Port
0
1
2
GPxCON REGISTERS
GPxCON are the Port x control registers, which select the
function of each pin of Port x as described in Table 104.
Table 103.GPXCON Registers
Name
GP0CON0
GP1CON
GP2CON
Pin
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P2.0
P2.1
Address
0xFFFF0D00
0xFFFF0D04
0xFFFF0D08
00
GPIO
GPIO
GPIO
GPIO
GPIO/IRQ0
GPIO
GPIO
GPIO/IRQ1
GPIO
GPIO
GPIO
GPIO
GPIO/IRQ3
GPIO
GPIO/IRQ2
GPIO/IRQ3
Configuration via GPxCON
01
SS (SPI slave select)
SCLK/SCL (Serial clock/SPI clock)
MISO (SPI—master in/slave out)
MOSI (SPI—master out/slave in)
PWM1 (PWM Input 1)
SIN (serial input)
SOUT (serial output)
PWMsync (PWM sync input pin)
PWMtrip (PWM trip input pin)
PWM2 (PWM Input 2)
PWM3 (PWM Input 3)
PWM4 (PWM Input 4)
PWM0 (PWM Input 0)
PWM5 (PWM Input 5)
Default Value
0x00000000
0x00000000
0x00000000
Access
R/W
R/W
R/W
Rev. PrA | Page 94 of 100
Table 104. GPxCON MMR Bit Descriptions
Bit
31:30
29:28
27:26
25:24
23:22
21:20
19:18
17:16
15:14
13:12
11:10
9:8
7:6
5:4
3:2
1:0
GPxDAT REGISTERS
GPxDAT are Port x configuration and data registers. They
configure the direction of the GPIO pins of Port x, set the
output value for the pins that are configured as output, and
store the input value of the pins that are configured as input.
Table 105. GPxDAT Registers
Name
GP0DAT
GP1DAT
GP2DAT
Table 106. GPxDAT MMR Bit Descriptions
Bit
31:24
23:16
15:8
7:0
GPxSET REGISTERS
GPxSET are data set Port x registers.
Table 107. GPxSET Registers
Name
GP0SET
GP1SET
GP2SET
Description
Reserved.
Reserved.
Reserved.
Select function of Px.6 pin.
Reserved.
Select function of Px.5 pin.
Reserved.
Select function of Px.4 pin.
Reserved.
Select function of Px.3 pin.
Reserved.
Select function of Px.2 pin.
Reserved.
Select function of Px.1 pin.
Reserved.
Select function of Px.0 pin.
Description
Direction of the Data.
Port x Data Output.
Reflect the State of Port x Pins at Reset (Read Only).
Port x Data Input (Read Only).
Set to 1 by user to configure the GPIO pin as an
output.
Cleared to 0 by user to configure the GPIO pin as an
input.
Address
0xFFFF0D20
0xFFFF0D30
0xFFFF0D40
Address
0xFFFF0D24
0xFFFF0D34
0xFFFF0D44
Preliminary Technical Data
Default Value
0x000000XX
0x000000XX
0x000000XX
Default Value
0x000000XX
0x000000XX
0x000000XX
W
W
W
Access
R/W
R/W
R/W
Access