aduc7062 Analog Devices, Inc., aduc7062 Datasheet - Page 90

• Manufacturer Part Number: aduc7062
• Description: Low-power, Precision Analog Microcontroller, Dual ?-? Adcs, Flash/ee, Arm7tdmi
• Manufacturer: Analog Devices, Inc.

ADuC7060/ADuC7061/ADuC7062
SPI REGISTERS
The following MMR registers control the SPI interface: SPISTA, SPIRX, SPITX, SPIDIV, and SPICON.
SPI Status Register
Name:
Address:
Default value:
Access:
Function:
Table 100. SPISTA MMR Bit Designations
Bit
15:12
11
10:8
7
6
5
4
3:1
0
Name
SPIREX
SPIRXFSTA[2:0]
SPIFOF
SPIRXIRQ
SPITXIRQ
SPITXUF
SPITXFSTA[2:0]
SPIISTA
SPISTA
0xFFFF0A00
0x00000000
Read/write
This 32-bit MMR contains the status of the SPI interface in both master and slave modes.
Description
Reserved bits.
SPI Rx FIFO excess bytes present. This bit is set when there are more bytes in the Rx FIFO than indicated in the
SPIRXMDE bits in SPICON
This bit is cleared when the number of bytes in the FIFO is equal or less than the number in SPIRXMDE.
SPI Rx FIFO Status Bits.
[000] = Rx FIFO is empty
[001] = 1 valid byte in the FIFO
[010] = 2 valid byte in the FIFO
[011] = 3 valid byte in the FIFO
[100] = 4 valid byte in the FIFO
Clear this bit to disable clock stretching.
SPI Rx FIFO Overflow Status Bit.
Set when the Rx FIFO was already full when new data was loaded to the FIFO. This bit generates an interrupt
except when SPIRFLH is set in SPICON.
Cleared when the SPISTA register is read.
SPI Rx IRQ Status Bit.
Set when a receive interrupt occurs. This bit is set when SPITMDE in SPICON is cleared and the required
number of bytes have been received.
Cleared when the SPISTA register is read.
SPI Tx IRQ Status Bit.
Set when a transmit interrupt occurs. This bit is set when SPITMDE in SPICON is set and the required number
of bytes have been transmitted.
Cleared when the SPISTA register is read.
SPI Tx FIFO Underflow.
This bit is set when a transmit is initiated without any valid data in the Tx FIFO. This bit generates an interrupt
except when SPITFLH is set in SPICON.
Cleared when the SPISTA register is read.
SPI Tx FIFO Status Bits.
[000] = Tx FIFO is empty.
[001] = 1 valid byte in the FIFO.
[010] = 2 valid byte in the FIFO.
[011] = 3 valid byte in the FIFO.
[100] = 4 valid byte in the FIFO.
Clear this bit to enable 7-bit address mode
SPI Interrupt Status Bit.
Set to 1 when an SPI based interrupt occurs.
Cleared after reading SPISTA.
Rev. PrA | Page 90 of 100
Preliminary Technical Data