peb3456e Infineon Technologies Corporation, peb3456e Datasheet - Page 141
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peb3456e
Manufacturer Part Number
peb3456e
Description
Channelized T3 Termination, With Ds3 Framer, M13 Multiplexer, T1/e1 Framers And 256-channel Hdlc/ppp Controller
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEB3456E.pdf
(424 pages)
- Current page: 141 of 424
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4.13.2.3 Facility Data Link Interrupts
Receive Interrupts
•
RSA
SSM
RPF
RME
ISF
PORT
Data Sheet
LAST
15
14
0
0
Receive S
S
SSM Data Valid
This bit is set, when a new synchronization status message has been
received. The synchronization status message is stored in register
RSAW4.
Receive Pool Full
This bit is set, when 32 bytes of a frame have been received and are
stored in the receive FIFO. The frame is not yet completely received.
Receive Message End
This bit is set, when one complete message of length less than 32 bytes
or the last part of a frame at least 32 bytes long is stored in the receive
FIFO. The number of bytes in RFF.RFIFO can be determined reading
the port status register PSR.
Incorrect Synchronization Format
This bit is set, when no eight consecutive ‘1’s are detected within 32 bits
in BOM mode. Only valid if BOM receiver has been activated.
Port Number
0..27 The port number the interrupt vector is associated with.
a
data in RSAW1 - RSAW3 is valid.
0
RSA SSM RPF RME
11
a
Data Valid
10
9
8
141
ISF
7
6
01
B
5
4
Functional Description
PORT(4:0)
PEB 3456 E
05.2001
0
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