peb3456e Infineon Technologies Corporation, peb3456e Datasheet - Page 150
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peb3456e
Manufacturer Part Number
peb3456e
Description
Channelized T3 Termination, With Ds3 Framer, M13 Multiplexer, T1/e1 Framers And 256-channel Hdlc/ppp Controller
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEB3456E.pdf
(424 pages)
- Current page: 150 of 424
- Download datasheet (6Mb)
bridge can be accessed through the PCI Interface directly after a system reset. In this
case the PCI configuration space contains the default values.
5.2.1
The EEPROM contents can also be controlled (read and write) by the software. For this,
a special EEPROM control register is implemented as part of the PCI configuration
space. To start a read/write transaction to an connected EEPROM, you have to set the
command, the byte address (for read-/write data commands), the data to be written and
the start indication by writing to the EEPROM control register SPI in the PCI
configuration space. If the interface detects SPI.START asserted (= ‘1’), it interprets the
command and starts the read-/write transaction to the connected EEPROM. After the
transaction has finished, the EEPROM control module deasserts the start bit. If the
command was a read command (Read Status Register, Read Data from Memory Array),
the byte that was read out of the EEPROM is available in the data register. For
transactions started with the EEPROM Control register, the interface does not check if
an EEPROM is connected to the SPI bus, because the EEPROM is full passive. A full
functional description of the SPI commands and their usage as well as a description of
the EEPROMs status register can be found in the description of the EEPROM that will
be selected by a board vendor.
Byte Address
For read and write transaction to the connected EEPROM, the byte address must be
written in this register before the transaction is started.
Data
For the write status register transaction and the write data to memory array transactions,
the data that has to be written to the EEPROM must be written to this register before the
transaction is started. After a read status register transaction or a read data from memory
array transaction has finished (Bit SPI.START is deasserted), the byte received from the
EEPROM is available in this register.
Start
To start the EEPROM transaction defined via register SPI the bit SPI.START must be
set to ‘1’ by a write transaction through the PCI interface. After the transaction is finished,
the EEPROM start bit is deasserted by the EEPROM interface controller. This signal has
to be polled by system software.
5.2.2
The TE3-CHATT selects an external EEPROM by pulling SPCS low. The eight bit read
sequence is transmitted followed by the eight bit address. After the read instruction and
Data Sheet
Accesses to a SPI EEPROM
SPI Read Sequence
150
Interface Description
PEB 3456 E
05.2001
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