peb3456e Infineon Technologies Corporation, peb3456e Datasheet - Page 263
![no-image](/images/no-image-200.jpg)
peb3456e
Manufacturer Part Number
peb3456e
Description
Channelized T3 Termination, With Ds3 Framer, M13 Multiplexer, T1/e1 Framers And 256-channel Hdlc/ppp Controller
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEB3456E.pdf
(424 pages)
- Current page: 263 of 424
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8.9.2.1
D3CLKCS
DS3 Clock Configuration and Status Register
Access
Address
Reset Value
Note: When this register is reset, it takes aproximately 150 ns to fully reset the recevie
RCA
TCA
RRX
RTX
Data Sheet
15
0
and transmit clock units. During this time, write access to DS3 registers is not
guaranteed. As this reset delay is difficult to gurantee in software, it is
recommended to read this register to verify DS3 clock activity before writing to any
DS3 registers.
0
M13 Transmit Registers
0
: read/write
: 180
: 0000
Receive Clock Activity
This bit monitors the receive clock activity (RC44).
0
1
Transmit Clock Activity
This bit monitors the transmit clock activity (TC44).
0
1
Reset Receiver Clock Unit
This bit resets the receivers clock unit.
0
1
Reset Transmitter Clock Unit
This bit resets the transmitters clock unit.
0
H
H
(PCI), 40
No receive DS3 clock since last read of this register. This bit is
set to ‘0’ approx. 125 s after the last active clock was detected.
At least one receive DS3 clock since last read of this register.
No transmit DS3 clock since last read of this register. This bit is
set to ‘0’ approx. 125 s after the last active clock was detected.
At least one transmit DS3 clock since last read of this register.
Normal operation.
Reset DS3 receiver clock unit. This bit is self clearing.
0
0
H
(Local bus)
0
0
263
0
RCA TCA RRX RTX T2RL R2TL TXLT
6
5
4
Register Description
3
2
PEB 3456 E
1
05.2001
0
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