peb3456e Infineon Technologies Corporation, peb3456e Datasheet - Page 142
![no-image](/images/no-image-200.jpg)
peb3456e
Manufacturer Part Number
peb3456e
Description
Channelized T3 Termination, With Ds3 Framer, M13 Multiplexer, T1/e1 Framers And 256-channel Hdlc/ppp Controller
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEB3456E.pdf
(424 pages)
- Current page: 142 of 424
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Transmit Interrupts
•
TXSA
ALLS
XDU
XPR
PORT
Data Sheet
LAST
15
14
1
0
Transmit S
The ’Transmit S
XSAW1 - XSAW3 has been sent N times, where N is defined prior to
transmission in XSAW3.XSAV.
All Sent
The ’All Sent’ interrupt vector is generated, when the last bit of a frame
to be transmitted is completely sent out and XFF.XFIFO is empty.
Transmit Data Underrun
The ’Transmit Data Underrun’ interrupt vector is generated, when the
transmit FIFO runs out of data during transmission of a frame. The
signalling controller terminates the affected frame with an abort
sequence.
Transmit Pool Ready
The ’Transmit Pool Ready’ interrupt vector is generated, when a new
data block of up to 32 bytes can be written to transmit FIFO. ’Transmit
Pool Ready’ is the fastest way to access the transmit FIFO. It has to be
used for transmission of long frames, back-to-back frames or frames
with shared flag.
Port Number
0..27 The port number the interrupt vector is associated with.
0
0
a
Data Sent
TXSA ALLS XDU XPR
10
a
Data Sent’ is generated, when S
9
8
142
7
6
01
B
5
4
Functional Description
PORT(4:0)
a
data stored in
PEB 3456 E
05.2001
0
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