peb3456e Infineon Technologies Corporation, peb3456e Datasheet - Page 283
![no-image](/images/no-image-200.jpg)
peb3456e
Manufacturer Part Number
peb3456e
Description
Channelized T3 Termination, With Ds3 Framer, M13 Multiplexer, T1/e1 Framers And 256-channel Hdlc/ppp Controller
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEB3456E.pdf
(424 pages)
- Current page: 283 of 424
- Download datasheet (6Mb)
D3RTUC
DS3 Receive Test Unit Control Register
Access
Address
Reset Value
EN
TUDS2
TUDS1
TURM
Data Sheet
15
0
0
0
: read/write
: 1D0
: 0000
Enable Test Unit Receive Clock
This bit enables the receive clock of the test unit. The clock speed is
dependent on the selected test mode.
0
1
Test Unit DS2 Group
This bit field selects the DS2 group the test unit is attached to. Only valid
if TURM is 10
0..6
Test Unit DS1/E1 Tributary
This bit field selects the DS1/E1 tributary the test unit is attached to. Only
valid if TURM is 00
0..3
Test Unit Receive Mode
This bit field selects the interface the test unit is attached to.
00
01
10
11
B
B
B
B
0
H
H
(PCI), 68
Receive clock disabled.
Receive clock enabled.
Selects DS2 group 0..6.
DS1/E1 tributary
DS1/E1 tributary (unframed)
DS2 tributary (unframed, bypass M12)
DS2 payload (framed)
DS3 payload (framed)
0
B
0
, 01
H
(Local bus)
B
B
0
, or 00
. The DS2 group is selected via TUDS2.
0
B
283
.
EN
7
6
TUDS2(2:0)
4
Register Description
TUDS1(1:0)
3
2
PEB 3456 E
1
TURM
05.2001
0
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