peb3456e Infineon Technologies Corporation, peb3456e Datasheet - Page 278

• Manufacturer Part Number: peb3456e
• Description: Channelized T3 Termination, With Ds3 Framer, M13 Multiplexer, T1/e1 Framers And 256-channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

FFM
IRCK
IRD
URD
Data Sheet
F Framing Mode
This bit selects the F-bit error condition which triggers the DS3 framer to
start a new frame search.
0
1
Invert Receive Clock
This bit sets the clock edge for data sampling.
0
1
Invert Receive Data
This bit enables inversion of receive data.
0
1
Unipolar Receive Data
This bit sets the port mode to dual-rail mode or unipolar mode.
0
1
A new frame search is started when 3 out of 8 contiguous F-bits
are in error.
A new frame search is started when 3 out of 16 contiguous F-bits
are in error.
Sample data on the rising edge of receive clock.
Sample data on the falling edge of receive clock.
Receive data is logic high (not inverted).
Receive data is logic low (inverted).
B3ZS (dual rail data input)
Unipolar mode (single rail data input)
278
Register Description
PEB 3456 E
05.2001