peb3456e Infineon Technologies Corporation, peb3456e Datasheet - Page 372

• Manufacturer Part Number: peb3456e
• Description: Channelized T3 Termination, With Ds3 Framer, M13 Multiplexer, T1/e1 Framers And 256-channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

HND
Handshake Register
Access
Address
Reset Value
Note: Receive command (bit 8) and transmit commands (bit 5 down to bit 0) can not be
RMC
ABORT
XRES
XREP
Data Sheet
15
0
issued at the same time. Doing so will cause the facility data link to omit the
transmit commands.
0
0
: write
: 07
: 0000
Receive Message Complete
This bit is a confirmation from CPU that a data block has been read from
RFIFO following a ’Receive Pool Full’ or ’Receive Message End’
interrupt vector and that the occupied page can now be released.
0
1
Note: If this bit is set, the low byte (transmit commands) of the register
Abort Frame
Setting this bit aborts HDLC frames which are transmitted.
0
1
Transmitter Reset
This bit resets the signalling controller transmit. However, the contents
of the control register will not be reset.
0
1
Transmission Repeat
Setting this bit together with bit XTF indicates that the contents stored in
XFF.XFIFO shall be repeatedly transmitted by the TE3-CHATT.
0
0
H
H
No function
Release page of receive FIFO.
HND is ignored.
Normal operation
Abort HDLC frame.
Normal operation
Transmitter reset
No cyclic transmission.
0
0
0
RMC
8
372
0
ABORT
XRES XREP OBI
5
4
Register Description
3
XHF
2
PEB 3456 E
XTF XME
1
05.2001
0