peb3456e Infineon Technologies Corporation, peb3456e Datasheet - Page 40
peb3456e
Manufacturer Part Number
peb3456e
Description
Channelized T3 Termination, With Ds3 Framer, M13 Multiplexer, T1/e1 Framers And 256-channel Hdlc/ppp Controller
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEB3456E.pdf
(424 pages)
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Data Sheet
Pin No.
C15
M24
N26
C12
C14
D14
Symbol
RSPO
or
TRCLK
TRD
TTCLK
TTD
TC44
TC44O
Output (O)
Input (I)
O
O
O
O
I
I
I
40
Function
Regenerated Sync Pulse
RSPO supports debugging of the on-chip
T1/E1 framing function. If the T1/E1
framer achieved synchronization, the
internal synchronization pulse of one
selected T1/E1 framer can be monitored
on RSPO.
Test Receive Clock
In serial test mode the receive clock of
one selected T1/E1 interface is directly
feed to this output.
Test Receive Data
In serial test mode the incoming data
stream of one T1/E1 tributary is directly
feed to this output. Test receive data is
updated on the falling edge of the TRCLK.
Test Transmit Clock
In serial test mode this clock provides the
clock reference for the tributary provided
via TTD.
Test Transmit Data
In serial test mode the data stream
provided via TTD replaces the E1/T1 data
stream of the selected tributary. TTD is
sampled on the rising edge of the TTCLK.
DS3 Transmit Clock Input
This clock provides a reference clock for
the DS3 interface. The frequency of this
clock is nominally 44.736 MHz.
DS3 Transmit Clock Output
This output is a buffered version of the
selected transmit clock which can be set
to RC44 or TC44.
Pin Description
PEB 3456 E
05.2001
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