tmp88cs43fg TOSHIBA Semiconductor CORPORATION, tmp88cs43fg Datasheet - Page 112

• Manufacturer Part Number: tmp88cs43fg
• Description: 8 Bit Microcontroller Tlcs-870/x Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

10. 8-Bit TimerCounter 3 (TC3)
10.1 Configuration
TC3CR<TC3S>
Source
clock
Counter
TC3 pin input
Internal waveform
TC3DRA
TC3DRB
INTTC3
interrupt request
Read of TC3DRA
10.3.3 Capture Mode
sured with the internal clock. The capture mode is used to decode remote control signals, and identify AC50/60
Hz.
TC3DRB. Hereafter, whenever the rising edge is detected, the up-counter value is captured into TC3DRA and
the INTTC3 interrupt request is generated. The up-counter is cleared at this time. Generally, read TC3DRB and
TC3DRA during INTTC3 interrupt processing. After the up-counter is cleared, counting is continued and the
next up-counter value is captured into TC3DRB.
TC3DRA only, but not into TC3DRB. The INTTC3 interrupt request is generated. When the read instruction is
executed to TC3DRB at this time, the value at the completion of the last capture (FF immediately after a reset)
is read.
TC3CR<TC3CK>.
before the edge is detected. TC3DRA is set to FFH and the up-counter is cleared. Counting is continued by the
up-counter, but capture operation and overflow detection are stopped until TC3DRA is read. Generally, read
TC3DRB first because capture operation and overflow detection resume by reading TC3DRA.
Timer start
In the capture mode, the pulse width, frequency and duty cycle of the pulse input to the TC3 pin are mea-
When the falling edge of the TC3 input is detected after the timer starts, the up-counter value is captured into
When the rising edge is detected immediately after the timer starts, the up-counter value is captured into
The minimum input pulse width must be larger than one cycle width of the source clock programmed in
The INTTC3 interrupt request is generated if the up-counter overflow (FFH) occurs during capture operation
0
1
i-1
i
Capture
i
Figure 10-5 Capture Mode Timing Chart
i+1
k-1
k
0
Capture
k
1
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m-1
m m+1
Capture
m
n-1
n
0
Capture
n
1
2
3
Capture
FE
FE
FF
0
TMP88CS43FG
FF (Overflow)
1
Overflow
2
3