tmp88cs43fg TOSHIBA Semiconductor CORPORATION, tmp88cs43fg Datasheet - Page 148

• Manufacturer Part Number: tmp88cs43fg
• Description: 8 Bit Microcontroller Tlcs-870/x Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

driver)
13. Motor Control Circuit (PMD: Programmable motor
(01FDBH, 01FDAH)
(01FD7H, 01FD6H)
(01FD9H, 01FD8H)
(01FABH, 01FAAH)
(01FA7H, 01FA6H)
(01FA9H, 01FA8H)
Timer Circuit Registers [Addresses (PMD1 and PMD2)]
(01FA5H)
(01FD5H)
(01FA4H)
(01FD4H)
MTCRB
MTCRA
MCAP
CMP1
CMP2
Note: Read-modify-write instructions, such as a bit manipulation instruction, cannot access the MTCRB because it contains a
Note 1: When changing MTCRA<TMCK> setting, keep the MTCRA<TMEN> bit reset to “0” (disable mode timer).
Note 2: Read-modify-write instructions, such as a bit manipulation instruction, cannot access the MTCRA because it contains a
write-only bit.
7, 6, 5
DBOUT
write-only bit.
MCAP
7
5
3
2
1
4
3
2
1
0
7
7
DF
DF
DF
F
F
F
DBOUT
TMOF
CLCP
SWCP
PDCCP
TMCK
RBTM3
RBCL
SWRES
RBPDC
TMEN
DE
DE
DE
TMCK
E
E
E
6
–
6
Mode capture
DD
DD
DD
D
D
D
TMOF
Debug output
Mode timer overflow
Capture mode timer by over-
load protection
Capture mode timer in software
Capture mode timer by position
detection
Select clock
Reset mode timer from Timer 3
Reset mode timer by overload
protection
Reset mode timer in software
Reset mode timer by position
detection
Enable/disable mode timer
DC
DC
DC
C
C
C
5
5
DB
DB
DB
B
B
B
RBTM3
DA
DA
DA
A
A
A
4
–
4
D9
D9
D9
9
9
9
CLCP
RBCL
D8
D8
D8
3
3
8
8
8
Page 138
D7
D7
D7
7
7
7
SWRES
SWCP
0: Disable
1: Enable (P67 for PMD1, P77 for PMD2)
0: No overflow
1: Overflowed
0: Disable
1: Enable
0: No operation
1: Capture
0: Disable
1: Enable
000: fc/2
010: fc/2
100: fc/2
110: fc/2
001: fc/2
011: Reserved
101: Reserved
111: Reserved
0: Disable
1: Enable
0: Disable
1: Enable
0: No operation
1: Reset
0: Disable
1: Enable
0: Disable
1: Enable timer start
Position detection interval
2
2
D6
D6
D6
6
6
6
6
3
4
5
7
(3.2 μs at 20 MHz)
D5
D5
D5
(400 ns at 20 MHz)
(800 ns at 20 MHz)
(1.6 μs at 20 MHz)
(6.4 μs at 20 MHz)
PDCCP
RBPDC
5
5
5
1
1
D4
D4
D4
4
4
4
D3
D3
D3
TMEN
3
3
3
0
–
0
D2
D2
D2
2
2
2
(Initial value: 0*0*0 000*)
(Initial value: 0000 0000)
D1
D1
D1
1
1
1
D0
D0
D0
0
0
0
(Initial value: 0000 0000 0000
0000)
(Initial value: 0000 0000 0000
0000)
(Initial value: 0000 0000 0000
0000)
TMP88CS43FG
R/W
R/W
R/W
R/W
R/W
W
W
R
R