tmp88cs43fg TOSHIBA Semiconductor CORPORATION, tmp88cs43fg Datasheet - Page 69

• Manufacturer Part Number: tmp88cs43fg
• Description: 8 Bit Microcontroller Tlcs-870/x Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

6.2 Divider Output (
Time Base Timer Control Register
buzzer drive. Divider output is from
Data output
Approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric
The Divider Output is controlled by the Time Base Timer Control Register (TBTCR).
Note 1: Selection of divider output frequency (DVOCK) must be made while divider output is disabled (DVOEN="0"). Also, in other
Note 2: In case of using
Note 3: fc; High-frequency clock [Hz], *; Don't care
Note 4: Be sure to write "0" to TBTCR Register bit 4.
(00036H)
TBTCR
fc/2
fc/2
fc/2
fc/2
13
12
11
10
words, when changing the state of the divider output frequency from enabled (DVOEN="1") to disable(DVOEN="0"), do
not change the setting of the divider output frequency.
register.
,fc/2
,fc/2
,fc/2
,fc/2
14
13
12
11
Divider output control register
DVOCK
DVOEN
(a) configuration
7
Output latch
DVOEN
DVOCK
A
B
C
D
D
MPX
2
S
Y
TBTCR
Q
DVO
6
DVO
DVOCK
Divider output
enable / disable
Divider Output (
frequency selection: [Hz]
output, set output mode by P1CR register after setting the related port output latch to "1" by P1DR
DVOEN
)
5
DVO
Figure 6-3 Divider Output
DVO
pin.
"0"
)
4
(TBTEN)
Page 59
DVO pin
3
0: Disable
1: Enable
00
01
10
11
Port output latch
TBTCR<DVOEN>
DVO pin output
2
DV1CK=0
(TBTCK)
fc/2
fc/2
fc/2
1
fc/2
13
12
10
11
NORMAL, IDLE Mode
(b) Timing chart
0
(Initial value: 0000 0000)
DV1CK=1
fc/2
fc/2
fc/2
fc/2
14
13
12
11
TMP88CS43FG
R/W
R/W