tmp88cs43fg TOSHIBA Semiconductor CORPORATION, tmp88cs43fg Datasheet - Page 124

• Manufacturer Part Number: tmp88cs43fg
• Description: 8 Bit Microcontroller Tlcs-870/x Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

12. 8-Bit TimerCounter 5,6(TC5, 6)
12.1 Configuration
Example :Setting the timer mode with source clock fc/2
12.3 Function
12.3.1 8-Bit Timer Mode (TC5 and 6)
TC6CR<TC6S>
Internal
Source Clock
Counter
TTREG6
INTTC6 interrupt request
bit pulse width modulation (PWM) output modes. The TimerCounter 5 and 6 (TC5, 6) are cascadable to form a 16-
bit timer. The 16-bit timer has the operating modes such as the 16-bit timer, 16-bit event counter, 16-bit pulse width
modulation (PWM) output and 16-bit programmable pulse generation (PPG) modes.
The TimerCounter 5 and 6 have the 8-bit timer, 8-bit event counter, 8-bit programmable divider output (PDO), 8-
(TimerCounter6, fc = 20.0 MHz)
and the timer register j (TTREGj) value is detected, an INTTCj interrupt is generated and the up-counter is
cleared. After being cleared, the up-counter restarts counting.
In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter
Note 1: In the timer mode, fix TCjCR<TFFj> to 0. If not fixed, the
Note 2: In the timer mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the
Note 3: j = 5, 6
shift register configuration in the timer mode, the new value programmed in TTREGj is in effect immediately
after the programming. Therefore, if TTREGi is changed while the timer is running, an expected operation
may not be obtained.
?
Figure 12-2 8-Bit Timer Mode Timing Chart (TC6)
Table 12-3 Source Clock for TimerCounter 5, 6 (Internal Clock)
LD
DI
SET
EI
LD
LD
n
DV1CK = 0
fc/2
1
fc/2
fc/2
fc/2
11
NORMAL, IDLE mode
[Hz]
7
5
3
Source Clock
(TTREG6), 0AH
(EIRC). EF37
(TC6CR), 00010000B
(TC6CR), 00011000B
2
3
DV1CK = 1
fc/2
Match detect
fc/2
fc/2
fc/2
12
[Hz]
8
6
4
7
n-1
Page 114
Hz and generating an interrupt 64 μs later
n 0
fc = 20 MHz
DV1CK = 0
Resolution
500 ns
128 μs
: Sets the timer register (80 μs
: Enables INTTC6 interrupt.
: Sets the operating cock to fc/2
: Starts TC6.
Counter clear
8 μs
2 μs
1
PDOj, PWMj
2
Match detect
Repeated Cycle
fc = 20 MHz
DV1CK = 0
and
127.5 μs
32.6 ms
2.0 ms
510 μs
n-1
PPGj
n
÷
pins may output pulses.
2
7
, and 8-bit timer mode.
7
0
/fc = 0AH).
Counter clear
1
2
TMP88CS43FG
0